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drm/i915/reg: stop using implicit dev_priv in DSPCLK_GATE_D

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Remove the implicit dev_priv usage in DSPCLK_GATE_D register, and pass
it as parameter.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/41ca83573ca2d94bea568058f8cb8c35e814f8b1.1661855191.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2022-08-30 13:28:01 +03:00
parent 6d737d9bff
commit 3721d4fb76
6 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_display_power_well.c
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@ -1157,10 +1157,10 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
* (and never recovering) in this case. intel_dsi_post_disable() will * (and never recovering) in this case. intel_dsi_post_disable() will
* clear it when we turn off the display. * clear it when we turn off the display.
*/ */
val = intel_de_read(dev_priv, DSPCLK_GATE_D); val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
val &= DPOUNIT_CLOCK_GATE_DISABLE; val &= DPOUNIT_CLOCK_GATE_DISABLE;
val |= VRHUNIT_CLOCK_GATE_DISABLE; val |= VRHUNIT_CLOCK_GATE_DISABLE;
intel_de_write(dev_priv, DSPCLK_GATE_D, val); intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
/* /*
* Disable trickle feed and enable pnd deadline calculation * Disable trickle feed and enable pnd deadline calculation

4
drivers/gpu/drm/i915/display/intel_gmbus.c
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@ -183,12 +183,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
u32 val; u32 val;
/* When using bit bashing for I2C, this bit needs to be set to 1 */ /* When using bit bashing for I2C, this bit needs to be set to 1 */
val = intel_de_read(dev_priv, DSPCLK_GATE_D); val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
if (!enable) if (!enable)
val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
else else
val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
intel_de_write(dev_priv, DSPCLK_GATE_D, val); intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
} }
static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,

4
drivers/gpu/drm/i915/display/intel_overlay.c
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@ -211,9 +211,9 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
/* WA_OVERLAY_CLKGATE:alm */ /* WA_OVERLAY_CLKGATE:alm */
if (enable) if (enable)
intel_de_write(dev_priv, DSPCLK_GATE_D, 0); intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);
else else
intel_de_write(dev_priv, DSPCLK_GATE_D, intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),
OVRUNIT_CLOCK_GATE_DISABLE); OVRUNIT_CLOCK_GATE_DISABLE);
/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */

8
drivers/gpu/drm/i915/display/vlv_dsi.c
View File

@ -822,9 +822,9 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
u32 val; u32 val;
/* Disable DPOunit clock gating, can stall pipe */ /* Disable DPOunit clock gating, can stall pipe */
val = intel_de_read(dev_priv, DSPCLK_GATE_D); val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
val |= DPOUNIT_CLOCK_GATE_DISABLE; val |= DPOUNIT_CLOCK_GATE_DISABLE;
intel_de_write(dev_priv, DSPCLK_GATE_D, val); intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
} }
if (!IS_GEMINILAKE(dev_priv)) if (!IS_GEMINILAKE(dev_priv))
@ -998,9 +998,9 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
vlv_dsi_pll_disable(encoder); vlv_dsi_pll_disable(encoder);
val = intel_de_read(dev_priv, DSPCLK_GATE_D); val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
val &= ~DPOUNIT_CLOCK_GATE_DISABLE; val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
intel_de_write(dev_priv, DSPCLK_GATE_D, val); intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
} }
/* Assert reset */ /* Assert reset */

2
drivers/gpu/drm/i915/i915_reg.h
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@ -1637,7 +1637,7 @@
#define DSTATE_PLL_D3_OFF (1 << 3) #define DSTATE_PLL_D3_OFF (1 << 3)
#define DSTATE_GFX_CLOCK_GATING (1 << 1) #define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0) #define DSTATE_DOT_CLOCK_GATING (1 << 0)
#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */

4
drivers/gpu/drm/i915/intel_pm.c
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@ -7994,7 +7994,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
OVCUNIT_CLOCK_GATE_DISABLE; OVCUNIT_CLOCK_GATE_DISABLE;
if (IS_GM45(dev_priv)) if (IS_GM45(dev_priv))
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate); intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate);
g4x_disable_trickle_feed(dev_priv); g4x_disable_trickle_feed(dev_priv);
} }
@ -8005,7 +8005,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
intel_uncore_write(uncore, RENCLK_GATE_D2, 0); intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
intel_uncore_write(uncore, DSPCLK_GATE_D, 0); intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0);
intel_uncore_write(uncore, RAMCLK_GATE_D, 0); intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
intel_uncore_write16(uncore, DEUC, 0); intel_uncore_write16(uncore, DEUC, 0);
intel_uncore_write(uncore, intel_uncore_write(uncore,