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dt-bindings: clock: renesas: Document RZ/G2UL SoC

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Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-03-15 14:29:15 +00:00 committed by Geert Uytterhoeven
parent 53367bd28f
commit 3733db1f77
1 changed files with 4 additions and 3 deletions
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7
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
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@ -10,7 +10,7 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
@ -23,8 +23,9 @@ description: |
properties:
compatible:
enum:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
reg:
maxItems: 1