tools headers: Synchronize KVM arch ABI headers
To pick up changes from these csets:da9a1446d2
("KVM: s390: provide a capability for AIS state migration")5c5196da4e
("KVM: arm/arm64: Support EL1 phys timer register access in set/get reg") None of which affects buildint tools/perf/. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Christoffer Dall <cdall@linaro.org> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Wang Nan <wangnan0@huawei.com> Link: https://lkml.kernel.org/n/tip-dd72s6izo4qdzt1isowlz8ji@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -152,6 +152,12 @@ struct kvm_arch_memory_slot {
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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/* PL1 Physical Timer Registers */
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#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
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#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
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#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
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/* Virtual Timer Registers */
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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@ -216,6 +222,7 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_ITS_CTRL_RESET 4
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/* KVM_IRQ_LINE irq field index values */
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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@ -196,6 +196,12 @@ struct kvm_arch_memory_slot {
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#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
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#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
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/* Physical Timer EL0 Registers */
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#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
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#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
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#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
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/* EL0 Virtual Timer Registers */
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#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
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#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
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#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
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#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
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@ -228,6 +234,7 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_ITS_CTRL_RESET 4
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/* Device Control API on vcpu fd */
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/* Device Control API on vcpu fd */
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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@ -931,6 +931,7 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_PPC_SMT_POSSIBLE 147
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#define KVM_CAP_PPC_SMT_POSSIBLE 147
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#define KVM_CAP_HYPERV_SYNIC2 148
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#define KVM_CAP_HYPERV_SYNIC2 148
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#define KVM_CAP_HYPERV_VP_INDEX 149
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#define KVM_CAP_HYPERV_VP_INDEX 149
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#define KVM_CAP_S390_AIS_MIGRATION 150
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#ifdef KVM_CAP_IRQ_ROUTING
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#ifdef KVM_CAP_IRQ_ROUTING
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