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drm/msm/dpu: Further cleanups for static inline functions

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Remove more static inline functions that are lightly used and/or
very simple and easy to build into the calling functions.

v3: Fix a nit from Sean Paul
v2: Removed another unused function from dpu_hw_lm.c and add back
dpu_crtc_get_client_type() since there was a question regarding
its usefulness.

Reviewed-by: Sean Paul <sean@poorly.run>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Jordan Crouse 2018-12-03 15:47:22 -07:00 committed by Rob Clark
parent 3d688410e6
commit 3804a98241
10 changed files with 13 additions and 71 deletions
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12
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View File

@ -46,12 +46,6 @@
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
struct drm_display_mode *mode)
{
return mode->hdisplay / cstate->num_mixers;
}
static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
{
struct msm_drm_private *priv = crtc->dev->dev_private;
@ -497,7 +491,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
{
struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
struct drm_display_mode *adj_mode = &state->adjusted_mode;
u32 crtc_split_width = _dpu_crtc_get_mixer_width(cstate, adj_mode);
u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
int i;
for (i = 0; i < cstate->num_mixers; i++) {
@ -952,7 +946,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
memset(pipe_staged, 0, sizeof(pipe_staged));
mixer_width = _dpu_crtc_get_mixer_width(cstate, mode);
mixer_width = mode->hdisplay / cstate->num_mixers;
_dpu_crtc_setup_lm_bounds(crtc, state);
@ -1193,7 +1187,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
cstate = to_dpu_crtc_state(crtc->state);
mode = &crtc->state->adjusted_mode;
out_width = _dpu_crtc_get_mixer_width(cstate, mode);
out_width = mode->hdisplay / cstate->num_mixers;
seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
mode->hdisplay, mode->vdisplay);

10
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
View File

@ -226,16 +226,6 @@ struct dpu_crtc_state {
#define to_dpu_crtc_state(x) \
container_of(x, struct dpu_crtc_state, base)
/**
* dpu_crtc_state_is_stereo - Is crtc virtualized with two mixers?
* @cstate: Pointer to dpu crtc state
* @Return: true - has two mixers, false - has one mixer
*/
static inline bool dpu_crtc_state_is_stereo(struct dpu_crtc_state *cstate)
{
return cstate->num_mixers == CRTC_DUAL_MIXERS;
}
/**
* dpu_crtc_frame_pending - retun the number of pending frames
* @crtc: Pointer to drm crtc object

2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
View File

@ -350,7 +350,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
if (phys_enc->split_role == ENC_ROLE_SOLO &&
dpu_crtc_state_is_stereo(dpu_cstate))
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
return BLEND_3D_H_ROW_INT;
return BLEND_3D_NONE;

11
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
View File

@ -44,14 +44,7 @@
#define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000
static inline int _dpu_encoder_phys_cmd_get_idle_timeout(
struct dpu_encoder_phys_cmd *cmd_enc)
{
return KICKOFF_TIMEOUT_MS;
}
static inline bool dpu_encoder_phys_cmd_is_master(
struct dpu_encoder_phys *phys_enc)
static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc)
{
return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
}
@ -723,7 +716,7 @@ static int dpu_encoder_phys_cmd_wait_for_vblank(
wait_info.wq = &cmd_enc->pending_vblank_wq;
wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc);
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
atomic_inc(&cmd_enc->pending_vblank_cnt);

9
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@ -736,13 +736,4 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
*/
void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
/**
* dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp
* @cfg: pointer to sspp cfg
*/
static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg)
{
return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) ||
test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features);
}
#endif /* _DPU_HW_CATALOG_H */

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
View File

@ -156,11 +156,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
}
static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer,
void *cfg)
{
}
static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
struct dpu_hw_lm_ops *ops,
unsigned long features)
@ -172,7 +167,6 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
ops->setup_alpha_out = dpu_hw_lm_setup_color3;
ops->setup_border_color = dpu_hw_lm_setup_border_color;
ops->setup_gc = dpu_hw_lm_gc;
};
static struct dpu_hw_blk_ops dpu_hw_ops;

5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
View File

@ -61,11 +61,6 @@ struct dpu_hw_lm_ops {
void (*setup_border_color)(struct dpu_hw_mixer *ctx,
struct dpu_mdss_color *color,
u8 border_en);
/**
* setup_gc : enable/disable gamma correction feature
*/
void (*setup_gc)(struct dpu_hw_mixer *mixer,
void *cfg);
};
struct dpu_hw_mixer {

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
View File

@ -661,7 +661,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
test_bit(DPU_SSPP_CSC_10BIT, &features))
c->ops.setup_csc = dpu_hw_sspp_setup_csc;
if (dpu_hw_sspp_multirect_enabled(c->cap))
if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) {

8
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -716,12 +716,6 @@ static const struct msm_kms_funcs kms_funcs = {
#endif
};
/* the caller api needs to turn on clock before calling it */
static inline void _dpu_kms_core_hw_rev_init(struct dpu_kms *dpu_kms)
{
dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
}
static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
{
struct msm_mmu *mmu;
@ -859,7 +853,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
pm_runtime_get_sync(&dpu_kms->pdev->dev);
_dpu_kms_core_hw_rev_init(dpu_kms);
dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);

18
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@ -430,24 +430,14 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
}
/**
* _dpu_plane_get_aspace: gets the address space
*/
static inline struct msm_gem_address_space *_dpu_plane_get_aspace(
struct dpu_plane *pdpu)
{
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
return kms->base.aspace;
}
static void _dpu_plane_set_scanout(struct drm_plane *plane,
struct dpu_plane_state *pstate,
struct dpu_hw_pipe_cfg *pipe_cfg,
struct drm_framebuffer *fb)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct msm_gem_address_space *aspace = _dpu_plane_get_aspace(pdpu);
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
struct msm_gem_address_space *aspace = kms->base.aspace;
int ret;
ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
@ -801,7 +791,7 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
struct drm_gem_object *obj;
struct msm_gem_object *msm_obj;
struct dma_fence *fence;
struct msm_gem_address_space *aspace = _dpu_plane_get_aspace(pdpu);
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
int ret;
if (!new_state->fb)
@ -810,7 +800,7 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
/* cache aspace */
pstate->aspace = aspace;
pstate->aspace = kms->base.aspace;
/*
* TODO: Need to sort out the msm_framebuffer_prepare() call below so