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clk: qcom: msm8996-cpu: Unify cluster order

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The power cluster comes before the performance cluster. Make
everything in the driver follow this order.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-4-y.oudjana@protonmail.com
This commit is contained in:
Yassine Oudjana
2022-06-21 20:06:18 +04:00
committed by Bjorn Andersson
parent de37e0214c
commit 382139bfd6
1 changed files with 32 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
drivers/clk/qcom/clk-cpu-8996.c
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@ -111,18 +111,6 @@ static const struct alpha_pll_config hfpll_config = {
.early_output_mask = BIT(3), .early_output_mask = BIT(3),
}; };
static struct clk_alpha_pll perfcl_pll = {
.offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "perfcl_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
};
static struct clk_alpha_pll pwrcl_pll = { static struct clk_alpha_pll pwrcl_pll = {
.offset = PWRCL_REG_OFFSET, .offset = PWRCL_REG_OFFSET,
.regs = prim_pll_regs, .regs = prim_pll_regs,
@ -135,6 +123,18 @@ static struct clk_alpha_pll pwrcl_pll = {
}, },
}; };
static struct clk_alpha_pll perfcl_pll = {
.offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "perfcl_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
};
static struct clk_fixed_factor pwrcl_pll_postdiv = { static struct clk_fixed_factor pwrcl_pll_postdiv = {
.mult = 1, .mult = 1,
.div = 2, .div = 2,
@ -181,20 +181,6 @@ static const struct alpha_pll_config altpll_config = {
.early_output_mask = BIT(3), .early_output_mask = BIT(3),
}; };
static struct clk_alpha_pll perfcl_alt_pll = {
.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_alt_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_alpha_pll pwrcl_alt_pll = { static struct clk_alpha_pll pwrcl_alt_pll = {
.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs, .regs = alt_pll_regs,
@ -209,6 +195,20 @@ static struct clk_alpha_pll pwrcl_alt_pll = {
}, },
}; };
static struct clk_alpha_pll perfcl_alt_pll = {
.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_alt_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
struct clk_cpu_8996_mux { struct clk_cpu_8996_mux {
u32 reg; u32 reg;
u8 shift; u8 shift;
@ -367,14 +367,14 @@ static const struct regmap_config cpu_msm8996_regmap_config = {
}; };
static struct clk_regmap *cpu_msm8996_clks[] = { static struct clk_regmap *cpu_msm8996_clks[] = {
&perfcl_pll.clkr,
&pwrcl_pll.clkr, &pwrcl_pll.clkr,
&perfcl_alt_pll.clkr, &perfcl_pll.clkr,
&pwrcl_alt_pll.clkr, &pwrcl_alt_pll.clkr,
&perfcl_smux.clkr, &perfcl_alt_pll.clkr,
&pwrcl_smux.clkr, &pwrcl_smux.clkr,
&perfcl_pmux.clkr, &perfcl_smux.clkr,
&pwrcl_pmux.clkr, &pwrcl_pmux.clkr,
&perfcl_pmux.clkr,
}; };
static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
@ -403,10 +403,10 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
return ret; return ret;
} }
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
/* Enable alt PLLs */ /* Enable alt PLLs */
clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);