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arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order

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The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.

Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-07-04 18:16:26 +02:00
parent 5b6d7c3c58
commit 3896b8f092
1 changed files with 9 additions and 9 deletions
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18
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
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@ -55,16 +55,16 @@
function = "i2c4";
};
scif3_pins: scif3 {
groups = "scif3_data", "scif3_ctrl";
function = "scif3";
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
scif3_pins: scif3 {
groups = "scif3_data", "scif3_ctrl";
function = "scif3";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
@ -76,16 +76,16 @@
status = "okay";
};
&scif3 {
pinctrl-0 = <&scif3_pins>;
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
&scif3 {
pinctrl-0 = <&scif3_pins>;
pinctrl-names = "default";
uart-has-rtscts;