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arm64: dts: renesas: r9a07g044: Add GbEthernet nodes

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Add Gigabit Ethernet{0,1} nodes to SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211013075647.32231-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-10-13 08:56:46 +01:00 committed by Geert Uytterhoeven
parent c534e655d5
commit 38ad23e15a
1 changed files with 40 additions and 0 deletions
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40
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
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@ -488,6 +488,46 @@
status = "disabled";
};
eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g044-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
<&cpg CPG_CORE R9A07G044_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g044-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
<&cpg CPG_CORE R9A07G044_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {
compatible = "renesas,r9a07g044-usbphy-ctrl",
"renesas,rzg2l-usbphy-ctrl";