Intel FB: more interlaced mode support
Intel FB: allow odd- and even-field-first in interlaced modes, and proper sync to vertical retrace Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: <sylvain.meyer@worldonline.fr> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Halasa
Linus Torvalds
parent
28ebe4f66b
commit
394d3af7ba
@ -376,7 +376,7 @@ int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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dinfo->vsync.pan_offset = offset;
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if ((var->activate & FB_ACTIVATE_VBL) &&
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!intelfbhw_enable_irq(dinfo, 0))
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!intelfbhw_enable_irq(dinfo))
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dinfo->vsync.pan_display = 1;
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else {
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dinfo->vsync.pan_display = 0;
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@ -1240,7 +1240,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
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u32 tmp;
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const u32 *dpll, *fp0, *fp1, *pipe_conf;
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const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
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u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
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u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
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u32 hsync_reg, htotal_reg, hblank_reg;
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u32 vsync_reg, vtotal_reg, vblank_reg;
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u32 src_size_reg;
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@ -1281,6 +1281,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
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fp0_reg = FPB0;
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fp1_reg = FPB1;
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pipe_conf_reg = PIPEBCONF;
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pipe_stat_reg = PIPEBSTAT;
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hsync_reg = HSYNC_B;
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htotal_reg = HTOTAL_B;
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hblank_reg = HBLANK_B;
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@ -1304,6 +1305,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
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fp0_reg = FPA0;
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fp1_reg = FPA1;
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pipe_conf_reg = PIPEACONF;
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pipe_stat_reg = PIPEASTAT;
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hsync_reg = HSYNC_A;
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htotal_reg = HTOTAL_A;
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hblank_reg = HBLANK_A;
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@ -1390,6 +1392,17 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
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OUTREG(vtotal_reg, *vt);
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OUTREG(src_size_reg, *ss);
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switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
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FB_VMODE_ODD_FLD_FIRST)) {
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case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
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OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
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break;
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case FB_VMODE_INTERLACED: /* even lines first */
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OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
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break;
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default: /* non-interlaced */
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OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
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}
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/* Enable pipe */
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OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
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@ -1955,71 +1968,72 @@ void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
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}
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}
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static irqreturn_t
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intelfbhw_irq(int irq, void *dev_id) {
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int handled = 0;
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static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
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{
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u16 tmp;
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struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
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spin_lock(&dinfo->int_lock);
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tmp = INREG16(IIR);
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tmp &= VSYNC_PIPE_A_INTERRUPT;
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if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
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tmp &= PIPE_A_EVENT_INTERRUPT;
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else
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tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
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if (tmp == 0) {
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spin_unlock(&dinfo->int_lock);
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return IRQ_RETVAL(handled);
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return IRQ_RETVAL(0); /* not us */
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}
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/* clear status bits 0-15 ASAP and don't touch bits 16-31 */
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OUTREG(PIPEASTAT, INREG(PIPEASTAT));
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OUTREG16(IIR, tmp);
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if (tmp & VSYNC_PIPE_A_INTERRUPT) {
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dinfo->vsync.count++;
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if (dinfo->vsync.pan_display) {
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dinfo->vsync.pan_display = 0;
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OUTREG(DSPABASE, dinfo->vsync.pan_offset);
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}
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wake_up_interruptible(&dinfo->vsync.wait);
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handled = 1;
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if (dinfo->vsync.pan_display) {
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dinfo->vsync.pan_display = 0;
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OUTREG(DSPABASE, dinfo->vsync.pan_offset);
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}
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dinfo->vsync.count++;
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wake_up_interruptible(&dinfo->vsync.wait);
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spin_unlock(&dinfo->int_lock);
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return IRQ_RETVAL(handled);
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return IRQ_RETVAL(1);
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}
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int
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intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
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int intelfbhw_enable_irq(struct intelfb_info *dinfo)
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{
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u16 tmp;
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if (!test_and_set_bit(0, &dinfo->irq_flags)) {
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if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
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"intelfb", dinfo)) {
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"intelfb", dinfo)) {
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clear_bit(0, &dinfo->irq_flags);
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return -EINVAL;
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}
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spin_lock_irq(&dinfo->int_lock);
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OUTREG16(HWSTAM, 0xfffe);
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OUTREG16(IMR, 0x0);
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OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
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spin_unlock_irq(&dinfo->int_lock);
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} else if (reenable) {
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u16 ier;
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OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
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OUTREG16(IMR, 0);
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} else
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spin_lock_irq(&dinfo->int_lock);
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ier = INREG16(IER);
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if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
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DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
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OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
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}
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spin_unlock_irq(&dinfo->int_lock);
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if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
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tmp = PIPE_A_EVENT_INTERRUPT;
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else
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tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
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if (tmp != INREG16(IER)) {
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DBG_MSG("changing IER to 0x%X\n", tmp);
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OUTREG16(IER, tmp);
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}
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spin_unlock_irq(&dinfo->int_lock);
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return 0;
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}
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void
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intelfbhw_disable_irq(struct intelfb_info *dinfo) {
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void intelfbhw_disable_irq(struct intelfb_info *dinfo)
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{
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if (test_and_clear_bit(0, &dinfo->irq_flags)) {
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if (dinfo->vsync.pan_display) {
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dinfo->vsync.pan_display = 0;
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@ -2051,7 +2065,7 @@ int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
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return -ENODEV;
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}
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ret = intelfbhw_enable_irq(dinfo, 0);
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ret = intelfbhw_enable_irq(dinfo);
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if (ret)
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return ret;
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@ -2061,7 +2075,6 @@ int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
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if (ret < 0)
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return ret;
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if (ret == 0) {
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intelfbhw_enable_irq(dinfo, 1);
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DBG_MSG("wait_for_vsync timed out!\n");
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return -ETIMEDOUT;
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}
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@ -280,6 +280,9 @@
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#define PIPEB_DSL 0x71000
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#define PIPEACONF 0x70008
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#define PIPEBCONF 0x71008
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#define PIPEASTAT 0x70024 /* bits 0-15 are "write 1 to clear" */
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#define PIPEBSTAT 0x71024
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#define PIPECONF_ENABLE (1 << 31)
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#define PIPECONF_DISABLE 0
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#define PIPECONF_DOUBLE_WIDE (1 << 30)
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@ -293,6 +296,31 @@
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#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
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#define PIPECONF_INTERLACE_MASK (7 << 21)
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/* enable bits, write 1 to enable */
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#define PIPESTAT_FIFO_UNDERRUN (1 << 31)
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#define PIPESTAT_CRC_ERROR_EN (1 << 29)
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#define PIPESTAT_CRC_DONE_EN (1 << 28)
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#define PIPESTAT_HOTPLUG_EN (1 << 26)
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#define PIPESTAT_VERTICAL_SYNC_EN (1 << 25)
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#define PIPESTAT_DISPLINE_COMP_EN (1 << 24)
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#define PIPESTAT_FLD_EVT_ODD_EN (1 << 21)
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#define PIPESTAT_FLD_EVT_EVEN_EN (1 << 20)
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#define PIPESTAT_TV_HOTPLUG_EN (1 << 18)
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#define PIPESTAT_VBLANK_EN (1 << 17)
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#define PIPESTAT_OVL_UPDATE_EN (1 << 16)
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/* status bits, write 1 to clear */
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#define PIPESTAT_HOTPLUG_STATE (1 << 15)
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#define PIPESTAT_CRC_ERROR (1 << 13)
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#define PIPESTAT_CRC_DONE (1 << 12)
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#define PIPESTAT_HOTPLUG (1 << 10)
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#define PIPESTAT_VSYNC (1 << 9)
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#define PIPESTAT_DISPLINE_COMP (1 << 8)
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#define PIPESTAT_FLD_EVT_ODD (1 << 5)
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#define PIPESTAT_FLD_EVT_EVEN (1 << 4)
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#define PIPESTAT_TV_HOTPLUG (1 << 2)
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#define PIPESTAT_VBLANK (1 << 1)
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#define PIPESTAT_OVL_UPDATE (1 << 0)
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#define DISPARB 0x70030
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#define DISPARB_AEND_MASK 0x1ff
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#define DISPARB_AEND_SHIFT 0
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@ -573,7 +601,7 @@ extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
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extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
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int height, u8 *data);
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extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
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extern int intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable);
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extern int intelfbhw_enable_irq(struct intelfb_info *dinfo);
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extern void intelfbhw_disable_irq(struct intelfb_info *dinfo);
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extern int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe);
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@ -207,6 +207,7 @@ struct fb_bitfield {
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#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
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#define FB_VMODE_INTERLACED 1 /* interlaced */
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#define FB_VMODE_DOUBLE 2 /* double scan */
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#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
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#define FB_VMODE_MASK 255
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#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
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