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iio: resolver: ad2s90: Fix alignment for DMA safety

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[ Upstream commit faa05ecb1349070d874810e161b653c2220e0006 ]

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes tag is probably not where the issue was first introduced, but
is likely to be far beyond the point where anyone considers
backporting this fix.

Fixes: 58f08b0af857 ("staging:iio:resolver:ad2s90 general cleanup")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-90-jic23@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jonathan Cameron 2022-05-08 18:57:09 +01:00 committed by Greg Kroah-Hartman
parent c00e752df9
commit 3af5ec85f4
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/resolver/ad2s90.c
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@ -24,7 +24,7 @@
struct ad2s90_state {
struct mutex lock; /* lock to protect rx buffer */
struct spi_device *sdev;
u8 rx[2] ____cacheline_aligned;
u8 rx[2] __aligned(IIO_DMA_MINALIGN);
};
static int ad2s90_read_raw(struct iio_dev *indio_dev,