media: rkisp1: regs: Rename CCL, ICCL and IRCL registers with VI_ prefix
The documentation names the CCL, ICCL and IRCL registers with a VI_ prefix, like the VI_ID and VI_DPCL registers. Fix the macro names accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com> Reviewed-by: Ricardo Ribalda <ribalda@chromium.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
240e92eaee
commit
3b430c2cf0
@ -525,20 +525,21 @@ static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
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readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
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val, val & RKISP1_CIF_ISP_OFF, 20, 100);
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rkisp1_write(rkisp1,
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RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
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RKISP1_CIF_IRCL);
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rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
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RKISP1_CIF_VI_IRCL_MIPI_SW_RST |
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RKISP1_CIF_VI_IRCL_ISP_SW_RST,
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RKISP1_CIF_VI_IRCL);
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rkisp1_write(rkisp1, 0x0, RKISP1_CIF_VI_IRCL);
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}
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static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
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{
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u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
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RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
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RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
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RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
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RKISP1_CIF_ICCL_DCROP_CLK;
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u32 val = RKISP1_CIF_VI_ICCL_ISP_CLK | RKISP1_CIF_VI_ICCL_CP_CLK |
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RKISP1_CIF_VI_ICCL_MRSZ_CLK | RKISP1_CIF_VI_ICCL_SRSZ_CLK |
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RKISP1_CIF_VI_ICCL_JPEG_CLK | RKISP1_CIF_VI_ICCL_MI_CLK |
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RKISP1_CIF_VI_ICCL_IE_CLK | RKISP1_CIF_VI_ICCL_MIPI_CLK |
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RKISP1_CIF_VI_ICCL_DCROP_CLK;
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rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
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rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ICCL);
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/* ensure sp and mp can run at the same time in V12 */
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if (rkisp1->media_dev.hw_revision == RKISP1_V12) {
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@ -1058,8 +1058,8 @@ static void rkisp1_ie_config(struct rkisp1_params *params,
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static void rkisp1_ie_enable(struct rkisp1_params *params, bool en)
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{
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if (en) {
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rkisp1_param_set_bits(params, RKISP1_CIF_ICCL,
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RKISP1_CIF_ICCL_IE_CLK);
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rkisp1_param_set_bits(params, RKISP1_CIF_VI_ICCL,
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RKISP1_CIF_VI_ICCL_IE_CLK);
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rkisp1_write(params->rkisp1, RKISP1_CIF_IMG_EFF_CTRL_ENABLE,
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RKISP1_CIF_IMG_EFF_CTRL);
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rkisp1_param_set_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
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@ -1067,8 +1067,8 @@ static void rkisp1_ie_enable(struct rkisp1_params *params, bool en)
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} else {
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rkisp1_param_clear_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
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RKISP1_CIF_IMG_EFF_CTRL_ENABLE);
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rkisp1_param_clear_bits(params, RKISP1_CIF_ICCL,
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RKISP1_CIF_ICCL_IE_CLK);
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rkisp1_param_clear_bits(params, RKISP1_CIF_VI_ICCL,
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RKISP1_CIF_VI_ICCL_IE_CLK);
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}
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}
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@ -210,7 +210,7 @@
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#define RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
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#define RKISP1_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
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/* CCL */
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/* VI_CCL */
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#define RKISP1_CIF_CCL_CIF_CLK_DIS BIT(2)
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/* VI_ISP_CLK_CTRL */
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#define RKISP1_CIF_CLK_CTRL_ISP_RAW BIT(0)
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@ -241,32 +241,32 @@
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#define RKISP1_CIF_CLK_CTRL_RSZS BIT(25)
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#define RKISP1_CIF_CLK_CTRL_MIPI BIT(26)
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#define RKISP1_CIF_CLK_CTRL_MARVINMI BIT(27)
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/* ICCL */
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#define RKISP1_CIF_ICCL_ISP_CLK BIT(0)
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#define RKISP1_CIF_ICCL_CP_CLK BIT(1)
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#define RKISP1_CIF_ICCL_RES_2 BIT(2)
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#define RKISP1_CIF_ICCL_MRSZ_CLK BIT(3)
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#define RKISP1_CIF_ICCL_SRSZ_CLK BIT(4)
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#define RKISP1_CIF_ICCL_JPEG_CLK BIT(5)
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#define RKISP1_CIF_ICCL_MI_CLK BIT(6)
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#define RKISP1_CIF_ICCL_RES_7 BIT(7)
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#define RKISP1_CIF_ICCL_IE_CLK BIT(8)
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#define RKISP1_CIF_ICCL_SIMP_CLK BIT(9)
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#define RKISP1_CIF_ICCL_SMIA_CLK BIT(10)
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#define RKISP1_CIF_ICCL_MIPI_CLK BIT(11)
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#define RKISP1_CIF_ICCL_DCROP_CLK BIT(12)
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/* IRCL */
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#define RKISP1_CIF_IRCL_ISP_SW_RST BIT(0)
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#define RKISP1_CIF_IRCL_CP_SW_RST BIT(1)
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#define RKISP1_CIF_IRCL_YCS_SW_RST BIT(2)
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#define RKISP1_CIF_IRCL_MRSZ_SW_RST BIT(3)
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#define RKISP1_CIF_IRCL_SRSZ_SW_RST BIT(4)
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#define RKISP1_CIF_IRCL_JPEG_SW_RST BIT(5)
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#define RKISP1_CIF_IRCL_MI_SW_RST BIT(6)
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#define RKISP1_CIF_IRCL_CIF_SW_RST BIT(7)
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#define RKISP1_CIF_IRCL_IE_SW_RST BIT(8)
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#define RKISP1_CIF_IRCL_SI_SW_RST BIT(9)
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#define RKISP1_CIF_IRCL_MIPI_SW_RST BIT(11)
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/* VI_ICCL */
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#define RKISP1_CIF_VI_ICCL_ISP_CLK BIT(0)
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#define RKISP1_CIF_VI_ICCL_CP_CLK BIT(1)
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#define RKISP1_CIF_VI_ICCL_RES_2 BIT(2)
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#define RKISP1_CIF_VI_ICCL_MRSZ_CLK BIT(3)
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#define RKISP1_CIF_VI_ICCL_SRSZ_CLK BIT(4)
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#define RKISP1_CIF_VI_ICCL_JPEG_CLK BIT(5)
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#define RKISP1_CIF_VI_ICCL_MI_CLK BIT(6)
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#define RKISP1_CIF_VI_ICCL_RES_7 BIT(7)
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#define RKISP1_CIF_VI_ICCL_IE_CLK BIT(8)
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#define RKISP1_CIF_VI_ICCL_SIMP_CLK BIT(9)
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#define RKISP1_CIF_VI_ICCL_SMIA_CLK BIT(10)
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#define RKISP1_CIF_VI_ICCL_MIPI_CLK BIT(11)
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#define RKISP1_CIF_VI_ICCL_DCROP_CLK BIT(12)
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/* VI_IRCL */
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#define RKISP1_CIF_VI_IRCL_ISP_SW_RST BIT(0)
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#define RKISP1_CIF_VI_IRCL_CP_SW_RST BIT(1)
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#define RKISP1_CIF_VI_IRCL_YCS_SW_RST BIT(2)
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#define RKISP1_CIF_VI_IRCL_MRSZ_SW_RST BIT(3)
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#define RKISP1_CIF_VI_IRCL_SRSZ_SW_RST BIT(4)
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#define RKISP1_CIF_VI_IRCL_JPEG_SW_RST BIT(5)
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#define RKISP1_CIF_VI_IRCL_MI_SW_RST BIT(6)
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#define RKISP1_CIF_VI_IRCL_CIF_SW_RST BIT(7)
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#define RKISP1_CIF_VI_IRCL_IE_SW_RST BIT(8)
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#define RKISP1_CIF_VI_IRCL_SI_SW_RST BIT(9)
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#define RKISP1_CIF_VI_IRCL_MIPI_SW_RST BIT(11)
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/* C_PROC_CTR */
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#define RKISP1_CIF_C_PROC_CTR_ENABLE BIT(0)
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@ -676,11 +676,11 @@
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/* CIF Registers */
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/* =================================================================== */
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#define RKISP1_CIF_CTRL_BASE 0x00000000
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#define RKISP1_CIF_CCL (RKISP1_CIF_CTRL_BASE + 0x00000000)
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#define RKISP1_CIF_VI_CCL (RKISP1_CIF_CTRL_BASE + 0x00000000)
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#define RKISP1_CIF_VI_ID (RKISP1_CIF_CTRL_BASE + 0x00000008)
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#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12 (RKISP1_CIF_CTRL_BASE + 0x0000000C)
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#define RKISP1_CIF_ICCL (RKISP1_CIF_CTRL_BASE + 0x00000010)
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#define RKISP1_CIF_IRCL (RKISP1_CIF_CTRL_BASE + 0x00000014)
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#define RKISP1_CIF_VI_ICCL (RKISP1_CIF_CTRL_BASE + 0x00000010)
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#define RKISP1_CIF_VI_IRCL (RKISP1_CIF_CTRL_BASE + 0x00000014)
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#define RKISP1_CIF_VI_DPCL (RKISP1_CIF_CTRL_BASE + 0x00000018)
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#define RKISP1_CIF_IMG_EFF_BASE 0x00000200
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