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arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

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The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Dinh Nguyen 2022-10-03 13:26:50 -05:00
parent 63fb606a59
commit 3b500ff37c
7 changed files with 7 additions and 0 deletions
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1
arch/arm/boot/dts/socfpga.dtsi
View File

@ -764,6 +764,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
altr,sysmgr-syscon = <&sysmgr 0x108 3>;
status = "disabled";
};

1
arch/arm/boot/dts/socfpga_arria10.dtsi
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@ -665,6 +665,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};

1
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
View File

@ -73,6 +73,7 @@
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&osc1 {

1
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
View File

@ -12,6 +12,7 @@
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&eccmgr {

1
arch/arm/boot/dts/socfpga_arria5.dtsi
View File

@ -23,6 +23,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {

1
arch/arm/boot/dts/socfpga_cyclone5.dtsi
View File

@ -23,6 +23,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {

1
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
View File

@ -18,5 +18,6 @@
&mmc0 { /* On-SoM eMMC */
bus-width = <8>;
clk-phase-sd-hs = <0>, <135>;
status = "okay";
};