arm64: implement dynamic shadow call stack for Clang
Implement dynamic shadow call stack support on Clang, by parsing the unwind tables at init time to locate all occurrences of PACIASP/AUTIASP instructions, and replacing them with the shadow call stack push and pop instructions, respectively. This is useful because the overhead of the shadow call stack is difficult to justify on hardware that implements pointer authentication (PAC), and given that the PAC instructions are executed as NOPs on hardware that doesn't, we can just replace them without breaking anything. As PACIASP/AUTIASP are guaranteed to be paired with respect to manipulations of the return address, replacing them 1:1 with shadow call stack pushes and pops is guaranteed to result in the desired behavior. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Sami Tolvanen <samitolvanen@google.com> Link: https://lore.kernel.org/r/20221027155908.1940624-4-ardb@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Ard Biesheuvel
Will Deacon
parent
9beccca098
commit
3b619e22c4
@ -2160,6 +2160,15 @@ config ARCH_NR_GPIO
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If unsure, leave the default value.
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config UNWIND_PATCH_PAC_INTO_SCS
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bool "Enable shadow call stack dynamically using code patching"
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# needs Clang with https://reviews.llvm.org/D111780 incorporated
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depends on CC_IS_CLANG && CLANG_VERSION >= 150000
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depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
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depends on SHADOW_CALL_STACK
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select UNWIND_TABLES
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select DYNAMIC_SCS
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endmenu # "Kernel Features"
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menu "Boot options"
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@ -77,10 +77,16 @@ branch-prot-flags-$(CONFIG_CC_HAS_SIGN_RETURN_ADDRESS) := -msign-return-address=
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# We enable additional protection for leaf functions as there is some
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# narrow potential for ROP protection benefits and no substantial
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# performance impact has been observed.
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PACRET-y := pac-ret+leaf
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# Using a shadow call stack in leaf functions is too costly, so avoid PAC there
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# as well when we may be patching PAC into SCS
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PACRET-$(CONFIG_UNWIND_PATCH_PAC_INTO_SCS) := pac-ret
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ifeq ($(CONFIG_ARM64_BTI_KERNEL),y)
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branch-prot-flags-$(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI) := -mbranch-protection=pac-ret+leaf+bti
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branch-prot-flags-$(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI) := -mbranch-protection=$(PACRET-y)+bti
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else
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branch-prot-flags-$(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET) := -mbranch-protection=pac-ret+leaf
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branch-prot-flags-$(CONFIG_CC_HAS_BRANCH_PROT_PAC_RET) := -mbranch-protection=$(PACRET-y)
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endif
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# -march=armv8.3-a enables the non-nops instructions for PAC, to avoid the
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# compiler to generate them and consequently to break the single image contract
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@ -5,6 +5,7 @@
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#ifdef __ASSEMBLY__
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#include <asm/asm-offsets.h>
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#include <asm/sysreg.h>
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#ifdef CONFIG_SHADOW_CALL_STACK
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scs_sp .req x18
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@ -24,6 +25,54 @@
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.endm
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#endif /* CONFIG_SHADOW_CALL_STACK */
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#else
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#include <linux/scs.h>
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#include <asm/cpufeature.h>
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#ifdef CONFIG_UNWIND_PATCH_PAC_INTO_SCS
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static inline bool should_patch_pac_into_scs(void)
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{
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u64 reg;
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/*
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* We only enable the shadow call stack dynamically if we are running
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* on a system that does not implement PAC or BTI. PAC and SCS provide
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* roughly the same level of protection, and BTI relies on the PACIASP
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* instructions serving as landing pads, preventing us from patching
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* those instructions into something else.
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*/
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reg = read_sysreg_s(SYS_ID_AA64ISAR1_EL1);
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if (SYS_FIELD_GET(ID_AA64ISAR1_EL1, APA, reg) |
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SYS_FIELD_GET(ID_AA64ISAR1_EL1, API, reg))
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return false;
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reg = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
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if (SYS_FIELD_GET(ID_AA64ISAR2_EL1, APA3, reg))
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return false;
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if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) {
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reg = read_sysreg_s(SYS_ID_AA64PFR1_EL1);
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if (reg & (0xf << ID_AA64PFR1_EL1_BT_SHIFT))
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return false;
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}
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return true;
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}
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static inline void dynamic_scs_init(void)
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{
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if (should_patch_pac_into_scs()) {
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pr_info("Enabling dynamic shadow call stack\n");
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static_branch_enable(&dynamic_scs_enabled);
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}
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}
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#else
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static inline void dynamic_scs_init(void) {}
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#endif
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int scs_patch(const u8 eh_frame[], int size);
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#endif /* __ASSEMBLY __ */
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#endif /* _ASM_SCS_H */
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@ -80,6 +80,8 @@ obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o
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obj-$(CONFIG_ARM64_MTE) += mte.o
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obj-y += vdso-wrap.o
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obj-$(CONFIG_COMPAT_VDSO) += vdso32-wrap.o
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obj-$(CONFIG_UNWIND_PATCH_PAC_INTO_SCS) += patch-scs.o
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CFLAGS_patch-scs.o += -mbranch-protection=none
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# Force dependency (vdso*-wrap.S includes vdso.so through incbin)
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$(obj)/vdso-wrap.o: $(obj)/vdso/vdso.so
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@ -462,6 +462,9 @@ SYM_FUNC_START_LOCAL(__primary_switched)
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bl early_fdt_map // Try mapping the FDT early
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mov x0, x20 // pass the full boot status
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bl init_feature_override // Parse cpu feature overrides
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#ifdef CONFIG_UNWIND_PATCH_PAC_INTO_SCS
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bl scs_patch_vmlinux
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#endif
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mov x0, x20
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bl finalise_el2 // Prefer VHE if possible
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ldp x29, x30, [sp], #16
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@ -41,7 +41,7 @@ static void init_irq_scs(void)
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{
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int cpu;
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if (!IS_ENABLED(CONFIG_SHADOW_CALL_STACK))
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if (!scs_is_enabled())
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return;
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for_each_possible_cpu(cpu)
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@ -15,9 +15,11 @@
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/moduleloader.h>
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#include <linux/scs.h>
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#include <linux/vmalloc.h>
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#include <asm/alternative.h>
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#include <asm/insn.h>
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#include <asm/scs.h>
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#include <asm/sections.h>
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void *module_alloc(unsigned long size)
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@ -514,5 +516,11 @@ int module_finalize(const Elf_Ehdr *hdr,
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if (s)
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apply_alternatives_module((void *)s->sh_addr, s->sh_size);
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if (scs_is_dynamic()) {
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s = find_section(hdr, sechdrs, ".init.eh_frame");
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if (s)
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scs_patch((void *)s->sh_addr, s->sh_size);
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}
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return module_init_ftrace_plt(hdr, sechdrs, me);
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}
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257
arch/arm64/kernel/patch-scs.c
Normal file
257
arch/arm64/kernel/patch-scs.c
Normal file
@ -0,0 +1,257 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2022 - Google LLC
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* Author: Ard Biesheuvel <ardb@google.com>
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*/
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#include <linux/bug.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/printk.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/scs.h>
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//
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// This minimal DWARF CFI parser is partially based on the code in
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// arch/arc/kernel/unwind.c, and on the document below:
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// https://refspecs.linuxbase.org/LSB_4.0.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html
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//
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#define DW_CFA_nop 0x00
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#define DW_CFA_set_loc 0x01
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#define DW_CFA_advance_loc1 0x02
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#define DW_CFA_advance_loc2 0x03
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#define DW_CFA_advance_loc4 0x04
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#define DW_CFA_offset_extended 0x05
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#define DW_CFA_restore_extended 0x06
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#define DW_CFA_undefined 0x07
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#define DW_CFA_same_value 0x08
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#define DW_CFA_register 0x09
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#define DW_CFA_remember_state 0x0a
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#define DW_CFA_restore_state 0x0b
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#define DW_CFA_def_cfa 0x0c
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#define DW_CFA_def_cfa_register 0x0d
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#define DW_CFA_def_cfa_offset 0x0e
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#define DW_CFA_def_cfa_expression 0x0f
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#define DW_CFA_expression 0x10
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#define DW_CFA_offset_extended_sf 0x11
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#define DW_CFA_def_cfa_sf 0x12
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#define DW_CFA_def_cfa_offset_sf 0x13
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#define DW_CFA_val_offset 0x14
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#define DW_CFA_val_offset_sf 0x15
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#define DW_CFA_val_expression 0x16
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#define DW_CFA_lo_user 0x1c
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#define DW_CFA_negate_ra_state 0x2d
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#define DW_CFA_GNU_args_size 0x2e
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#define DW_CFA_GNU_negative_offset_extended 0x2f
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#define DW_CFA_hi_user 0x3f
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extern const u8 __eh_frame_start[], __eh_frame_end[];
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enum {
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PACIASP = 0xd503233f,
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AUTIASP = 0xd50323bf,
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SCS_PUSH = 0xf800865e,
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SCS_POP = 0xf85f8e5e,
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};
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static void __always_inline scs_patch_loc(u64 loc)
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{
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u32 insn = le32_to_cpup((void *)loc);
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switch (insn) {
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case PACIASP:
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*(u32 *)loc = cpu_to_le32(SCS_PUSH);
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break;
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case AUTIASP:
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*(u32 *)loc = cpu_to_le32(SCS_POP);
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break;
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default:
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/*
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* While the DW_CFA_negate_ra_state directive is guaranteed to
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* appear right after a PACIASP/AUTIASP instruction, it may
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* also appear after a DW_CFA_restore_state directive that
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* restores a state that is only partially accurate, and is
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* followed by DW_CFA_negate_ra_state directive to toggle the
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* PAC bit again. So we permit other instructions here, and ignore
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* them.
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*/
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return;
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}
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dcache_clean_pou(loc, loc + sizeof(u32));
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}
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/*
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* Skip one uleb128/sleb128 encoded quantity from the opcode stream. All bytes
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* except the last one have bit #7 set.
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*/
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static int __always_inline skip_xleb128(const u8 **opcode, int size)
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{
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u8 c;
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do {
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c = *(*opcode)++;
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size--;
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} while (c & BIT(7));
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return size;
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}
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struct eh_frame {
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/*
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* The size of this frame if 0 < size < U32_MAX, 0 terminates the list.
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*/
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u32 size;
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/*
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* The first frame is a Common Information Entry (CIE) frame, followed
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* by one or more Frame Description Entry (FDE) frames. In the former
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* case, this field is 0, otherwise it is the negated offset relative
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* to the associated CIE frame.
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*/
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u32 cie_id_or_pointer;
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union {
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struct { // CIE
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u8 version;
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u8 augmentation_string[];
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};
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struct { // FDE
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s32 initial_loc;
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s32 range;
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u8 opcodes[];
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};
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};
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};
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static int noinstr scs_handle_fde_frame(const struct eh_frame *frame,
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bool fde_has_augmentation_data,
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int code_alignment_factor)
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{
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int size = frame->size - offsetof(struct eh_frame, opcodes) + 4;
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u64 loc = (u64)offset_to_ptr(&frame->initial_loc);
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const u8 *opcode = frame->opcodes;
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if (fde_has_augmentation_data) {
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int l;
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// assume single byte uleb128_t
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if (WARN_ON(*opcode & BIT(7)))
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return -ENOEXEC;
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l = *opcode++;
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opcode += l;
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size -= l + 1;
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}
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/*
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* Starting from 'loc', apply the CFA opcodes that advance the location
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* pointer, and identify the locations of the PAC instructions.
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*/
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while (size-- > 0) {
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switch (*opcode++) {
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case DW_CFA_nop:
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case DW_CFA_remember_state:
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case DW_CFA_restore_state:
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break;
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case DW_CFA_advance_loc1:
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loc += *opcode++ * code_alignment_factor;
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size--;
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break;
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case DW_CFA_advance_loc2:
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loc += *opcode++ * code_alignment_factor;
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loc += (*opcode++ << 8) * code_alignment_factor;
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size -= 2;
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break;
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case DW_CFA_def_cfa:
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case DW_CFA_offset_extended:
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size = skip_xleb128(&opcode, size);
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fallthrough;
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case DW_CFA_def_cfa_offset:
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case DW_CFA_def_cfa_offset_sf:
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case DW_CFA_def_cfa_register:
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case DW_CFA_same_value:
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case DW_CFA_restore_extended:
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case 0x80 ... 0xbf:
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size = skip_xleb128(&opcode, size);
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break;
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case DW_CFA_negate_ra_state:
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scs_patch_loc(loc - 4);
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break;
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case 0x40 ... 0x7f:
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// advance loc
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loc += (opcode[-1] & 0x3f) * code_alignment_factor;
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break;
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case 0xc0 ... 0xff:
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break;
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default:
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pr_err("unhandled opcode: %02x in FDE frame %lx\n", opcode[-1], (uintptr_t)frame);
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return -ENOEXEC;
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}
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}
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return 0;
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}
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int noinstr scs_patch(const u8 eh_frame[], int size)
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{
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const u8 *p = eh_frame;
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while (size > 4) {
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const struct eh_frame *frame = (const void *)p;
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bool fde_has_augmentation_data = true;
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int code_alignment_factor = 1;
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int ret;
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if (frame->size == 0 ||
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frame->size == U32_MAX ||
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frame->size > size)
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break;
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if (frame->cie_id_or_pointer == 0) {
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const u8 *p = frame->augmentation_string;
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/* a 'z' in the augmentation string must come first */
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fde_has_augmentation_data = *p == 'z';
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/*
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* The code alignment factor is a uleb128 encoded field
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* but given that the only sensible values are 1 or 4,
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* there is no point in decoding the whole thing.
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*/
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p += strlen(p) + 1;
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if (!WARN_ON(*p & BIT(7)))
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code_alignment_factor = *p;
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} else {
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ret = scs_handle_fde_frame(frame,
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fde_has_augmentation_data,
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code_alignment_factor);
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if (ret)
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return ret;
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}
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p += sizeof(frame->size) + frame->size;
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size -= sizeof(frame->size) + frame->size;
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}
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return 0;
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}
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asmlinkage void __init scs_patch_vmlinux(void)
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{
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if (!should_patch_pac_into_scs())
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return;
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WARN_ON(scs_patch(__eh_frame_start, __eh_frame_end - __eh_frame_start));
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icache_inval_all_pou();
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isb();
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}
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@ -144,7 +144,7 @@ static int init_sdei_scs(void)
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int cpu;
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int err = 0;
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if (!IS_ENABLED(CONFIG_SHADOW_CALL_STACK))
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if (!scs_is_enabled())
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return 0;
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for_each_possible_cpu(cpu) {
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@ -30,6 +30,7 @@
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#include <linux/efi.h>
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#include <linux/psci.h>
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#include <linux/sched/task.h>
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#include <linux/scs.h>
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#include <linux/mm.h>
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#include <asm/acpi.h>
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@ -42,6 +43,7 @@
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#include <asm/cpu_ops.h>
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#include <asm/kasan.h>
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#include <asm/numa.h>
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#include <asm/scs.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/smp_plat.h>
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@ -312,6 +314,8 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
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jump_label_init();
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parse_early_param();
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dynamic_scs_init();
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/*
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* Unmask asynchronous aborts and fiq after bringing up possible
|
||||
* earlycon. (Report possible System Errors once we can report this
|
||||
|
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Block a user