dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties
In most cases, the default values of DSI PHY tuning registers should be sufficient as they are fully optimized. However, in some cases where extreme board parasitics cause the eye shape to degrade, the override bits can be used to improve the signal quality. The general guidelines for DSI PHY tuning include: - High and moderate data rates may benefit from the drive strength and drive level tuning. - Drive strength tuning will affect the output impedance and may be used for matching optimization. - Drive level tuning will affect the output levels without affecting the impedance. The clock and data lanes have a calibration circuitry feature. The drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1643573719-32095-2-git-send-email-quic_rajeevny@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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@ -35,6 +35,38 @@ properties:
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Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
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connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
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qcom,phy-rescode-offset-top:
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$ref: /schemas/types.yaml#/definitions/int8-array
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minItems: 5
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maxItems: 5
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description:
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Integer array of offset for pull-up legs rescode for all five lanes.
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To offset the drive strength from the calibrated value in an increasing
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manner, -32 is the weakest and +31 is the strongest.
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items:
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minimum: -32
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maximum: 31
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qcom,phy-rescode-offset-bot:
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$ref: /schemas/types.yaml#/definitions/int8-array
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minItems: 5
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maxItems: 5
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description:
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Integer array of offset for pull-down legs rescode for all five lanes.
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To offset the drive strength from the calibrated value in a decreasing
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manner, -32 is the weakest and +31 is the strongest.
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items:
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minimum: -32
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maximum: 31
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qcom,phy-drive-ldo-level:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description:
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The PHY LDO has an amplitude tuning feature to adjust the LDO output
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for the HSTX drive. Use supported levels (mV) to offset the drive level
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from the default value.
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enum: [ 375, 400, 425, 450, 475, 500 ]
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required:
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- compatible
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- reg
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@ -64,5 +96,9 @@ examples:
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
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qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
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qcom,phy-drive-ldo-level = <400>;
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};
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...
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