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ARM: dts: uniphier: switch over to PSCI

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Use PSCI for enable-method instead of SoC specific implementation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2016-08-29 03:27:42 +09:00
parent 77896e4d05
commit 3bdba5ac18
7 changed files with 22 additions and 4 deletions
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5
arch/arm/boot/dts/uniphier-common32.dtsi
View File

@ -45,6 +45,11 @@
/include/ "skeleton.dtsi"
/ {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;

1
arch/arm/boot/dts/uniphier-ld4.dtsi
View File

@ -56,6 +56,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};

3
arch/arm/boot/dts/uniphier-pro4.dtsi
View File

@ -51,12 +51,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -64,6 +64,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};

3
arch/arm/boot/dts/uniphier-pro5.dtsi
View File

@ -51,12 +51,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -64,6 +64,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};

5
arch/arm/boot/dts/uniphier-pxs2.dtsi
View File

@ -51,12 +51,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -64,6 +64,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -71,6 +72,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -78,6 +80,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};

8
arch/arm/boot/dts/uniphier-sld3.dtsi
View File

@ -51,12 +51,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
@ -64,10 +64,16 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;

1
arch/arm/boot/dts/uniphier-sld8.dtsi
View File

@ -56,6 +56,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};