Merge tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Merge "ARM: imx: fixes for 3.19" from Shawn Guo: The i.MX fixes for 3.19: - One fix for incorrect i.MX25 SPI1 clock assignment in device tree, which causes system hang when accessing SPI1. - Correct i.MX6SX QSPI parent clock configuration to fix a kernel Oops. - Fix ULPI PHY reset modelling on imx51-babbage board to remove the dependency on bootloader for USB3317 ULPI PHY reset. - Correct video divider setting on i.MX6Q rev T0 1.0 to fix the issue that HDMI is not working at high resolution on T0 1.0. - One incremental fix for CODA960 VPU enabling in device tree to correct interrupt order. - LS1021A SCFG block works in BE mode, add device tree property big-endian to make it right. * tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling ARM: imx6sx: Set PLL2 as parent of QSPI clocks ARM: dts: imx25: Fix the SPI1 clocks ARM: clk-imx6q: fix video divider for rev T0 1.0 ARM: dts: imx6qdl: Fix CODA960 interrupt order ARM: ls1021a: dtsi: add 'big-endian' property for scfg node Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
3be8142951
@ -162,7 +162,7 @@
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x43fa4000 0x4000>;
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clocks = <&clks 62>, <&clks 62>;
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clocks = <&clks 78>, <&clks 78>;
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clock-names = "ipg", "per";
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interrupts = <14>;
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status = "disabled";
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@ -127,24 +127,12 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usbh1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1reg>;
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reg = <0>;
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regulator-name = "usbh1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usbotg_vbus: regulator@1 {
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reg_hub_reset: regulator@0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotgreg>;
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reg = <1>;
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regulator-name = "usbotg_vbus";
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reg = <0>;
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regulator-name = "hub_reset";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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@ -176,6 +164,7 @@
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reg = <0>;
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clocks = <&clks IMX5_CLK_DUMMY>;
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clock-names = "main_clk";
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reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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};
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};
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};
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@ -419,7 +408,7 @@
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&usbh1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1>;
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vbus-supply = <®_usbh1_vbus>;
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vbus-supply = <®_hub_reset>;
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fsl,usbphy = <&usbh1phy>;
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phy_type = "ulpi";
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status = "okay";
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@ -429,7 +418,6 @@
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dr_mode = "otg";
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disable-over-current;
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phy_type = "utmi_wide";
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vbus-supply = <®_usbotg_vbus>;
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status = "okay";
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};
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@ -335,8 +335,8 @@
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vpu: vpu@02040000 {
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compatible = "cnm,coda960";
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reg = <0x02040000 0x3c000>;
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interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bit", "jpeg";
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clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
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<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
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@ -142,6 +142,7 @@
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scfg: scfg@1570000 {
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compatible = "fsl,ls1021a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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clockgen: clocking@1ee1000 {
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@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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post_div_table[1].div = 1;
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post_div_table[2].div = 1;
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video_div_table[1].div = 1;
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video_div_table[2].div = 1;
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video_div_table[3].div = 1;
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}
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clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
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clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
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clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
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clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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}
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