i40e: remove unused defines
Remove all the unused defines as they are just dead weight. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Jesse Brandeburg
Jeff Kirsher
parent
fe21b6c3a6
commit
3c98f9ee6b
@ -60,17 +60,14 @@
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(((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
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#define I40E_DEFAULT_QUEUES_PER_VF 4
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#define I40E_MAX_VF_QUEUES 16
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#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
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#define i40e_pf_get_max_q_per_tc(pf) \
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(((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
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#define I40E_FDIR_RING 0
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#define I40E_FDIR_RING_COUNT 32
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#define I40E_MAX_AQ_BUF_SIZE 4096
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#define I40E_AQ_LEN 256
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#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
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#define I40E_MAX_USER_PRIORITY 8
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#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
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#define I40E_DEFAULT_MSG_ENABLE 4
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#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
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#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
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@ -92,10 +89,6 @@
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#define I40E_OEM_SNAP_SHIFT 16
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#define I40E_OEM_RELEASE_MASK 0x0000ffff
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/* The values in here are decimal coded as hex as is the case in the NVM map*/
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#define I40E_CURRENT_NVM_VERSION_HI 0x2
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#define I40E_CURRENT_NVM_VERSION_LO 0x40
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#define I40E_RX_DESC(R, i) \
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(&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
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#define I40E_TX_DESC(R, i) \
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@ -105,9 +98,6 @@
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#define I40E_TX_FDIRDESC(R, i) \
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(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
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/* default to trying for four seconds */
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#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
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/* BW rate limiting */
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#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
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#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
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@ -295,9 +285,6 @@ struct i40e_cloud_filter {
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u8 tunnel_type;
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};
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#define I40E_DCB_PRIO_TYPE_STRICT 0
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#define I40E_DCB_PRIO_TYPE_ETS 1
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#define I40E_DCB_STRICT_PRIO_CREDITS 127
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/* DCB per TC information data structure */
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struct i40e_tc_info {
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u16 qoffset; /* Queue offset from base queue */
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@ -357,15 +344,6 @@ struct i40e_ddp_old_profile_list {
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I40E_FLEX_SET_FSIZE(fsize) | \
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I40E_FLEX_SET_SRC_WORD(src))
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#define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
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I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
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I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
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#define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
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I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
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I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
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#define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
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I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
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I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
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#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
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@ -390,7 +368,6 @@ struct i40e_ddp_old_profile_list {
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#define I40E_L4_GLQF_ORT_IDX 35
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/* Flex PIT register index */
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#define I40E_FLEX_PIT_IDX_START_L2 0
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#define I40E_FLEX_PIT_IDX_START_L3 3
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#define I40E_FLEX_PIT_IDX_START_L4 6
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@ -531,7 +508,6 @@ struct i40e_pf {
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#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
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#define I40E_HW_PTP_L4_CAPABLE BIT(10)
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#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
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#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
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#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
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#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
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#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
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File diff suppressed because it is too large
Load Diff
@ -1455,10 +1455,6 @@ static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
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return gpio_val;
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}
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#define I40E_COMBINED_ACTIVITY 0xA
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#define I40E_FILTER_ACTIVITY 0xE
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#define I40E_LINK_ACTIVITY 0xC
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#define I40E_MAC_ACTIVITY 0xD
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#define I40E_FW_LED BIT(4)
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#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
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I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
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@ -6,10 +6,8 @@
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#include "i40e_type.h"
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#define I40E_DCBX_STATUS_NOT_STARTED 0
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#define I40E_DCBX_STATUS_IN_PROGRESS 1
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#define I40E_DCBX_STATUS_DONE 2
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#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
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#define I40E_DCBX_STATUS_DISABLED 7
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#define I40E_TLV_TYPE_END 0
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@ -24,7 +22,6 @@
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#define I40E_CEE_DCBX_OUI 0x001b21
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#define I40E_CEE_DCBX_TYPE 2
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#define I40E_CEE_SUBTYPE_CTRL 1
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#define I40E_CEE_SUBTYPE_PG_CFG 2
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#define I40E_CEE_SUBTYPE_PFC_CFG 3
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#define I40E_CEE_SUBTYPE_APP_PRI 4
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@ -105,9 +102,7 @@ struct i40e_cee_ctrl_tlv {
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struct i40e_cee_feat_tlv {
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struct i40e_cee_tlv_hdr hdr;
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u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
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#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
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#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
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#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
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u8 subtype;
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u8 tlvinfo[1];
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};
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@ -688,7 +688,6 @@ static void i40e_dbg_dump_vf_all(struct i40e_pf *pf)
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i40e_dbg_dump_vf(pf, i);
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}
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#define I40E_MAX_DEBUG_OUT_BUFFER (4096*4)
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/**
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* i40e_dbg_command_write - write into command datum
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* @filp: the opened file
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@ -32,8 +32,5 @@
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#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
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#define I40E_DEV_ID_SFP_I_X722 0x37D3
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#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
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(d) == I40E_DEV_ID_QSFP_B || \
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(d) == I40E_DEV_ID_QSFP_C)
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#endif /* _I40E_DEVIDS_H_ */
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@ -14,7 +14,6 @@ struct i40e_hw;
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#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
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#define I40E_HMC_PAGED_BP_SIZE 4096
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#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
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#define I40E_FIRST_VF_FPM_ID 16
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struct i40e_hmc_obj_info {
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u64 base; /* base addr in FPM */
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@ -6492,8 +6492,7 @@ out:
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return err;
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}
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#endif /* CONFIG_I40E_DCB */
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#define SPEED_SIZE 14
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#define FC_SIZE 8
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/**
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* i40e_print_link_message - print link up or down
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* @vsi: the VSI for which link needs a message
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@ -8950,13 +8949,6 @@ u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
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return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
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}
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/* We can see up to 256 filter programming desc in transit if the filters are
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* being applied really fast; before we see the first
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* filter miss error on Rx queue 0. Accumulating enough error messages before
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* reacting will make sure we don't cause flush too often.
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*/
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#define I40E_MAX_FD_PROGRAM_ERROR 256
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/**
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* i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
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* @pf: board private structure
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@ -26,7 +26,6 @@ do { \
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#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
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#define rd32(a, reg) readl((a)->hw_addr + (reg))
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#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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#define rd64(a, reg) readq((a)->hw_addr + (reg))
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#define i40e_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT)
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File diff suppressed because it is too large
Load Diff
@ -18,10 +18,7 @@
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#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
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#define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */
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#define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */
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#define I40E_ITR_100K 10 /* all values below must be even */
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#define I40E_ITR_50K 20
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#define I40E_ITR_20K 50
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#define I40E_ITR_18K 60
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#define I40E_ITR_8K 122
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#define I40E_MAX_ITR 8160 /* maximum value as per datasheet */
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#define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC)
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@ -52,9 +49,6 @@ static inline u16 i40e_intrl_usec_to_reg(int intrl)
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else
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return 0;
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}
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#define I40E_INTRL_8K 125 /* 8000 ints/sec */
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#define I40E_INTRL_62K 16 /* 62500 ints/sec */
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#define I40E_INTRL_83K 12 /* 83333 ints/sec */
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#define I40E_QUEUE_END_OF_LIST 0x7FF
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@ -73,7 +67,6 @@ enum i40e_dyn_idx_t {
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/* these are indexes into ITRN registers */
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#define I40E_RX_ITR I40E_IDX_ITR0
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#define I40E_TX_ITR I40E_IDX_ITR1
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#define I40E_PE_ITR I40E_IDX_ITR2
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/* Supported RSS offloads */
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#define I40E_DEFAULT_RSS_HENA ( \
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@ -193,13 +186,6 @@ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */
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#define I40E_RX_INCREMENT(r, i) \
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do { \
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(i)++; \
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if ((i) == (r)->count) \
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i = 0; \
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r->next_to_clean = i; \
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} while (0)
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#define I40E_RX_NEXT_DESC(r, i, n) \
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do { \
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@ -209,11 +195,6 @@ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
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(n) = I40E_RX_DESC((r), (i)); \
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} while (0)
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#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
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do { \
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I40E_RX_NEXT_DESC((r), (i), (n)); \
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prefetch((n)); \
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} while (0)
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#define I40E_MAX_BUFFER_TXD 8
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#define I40E_MIN_TX_LEN 17
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@ -262,15 +243,12 @@ static inline unsigned int i40e_txd_use_count(unsigned int size)
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/* Tx Descriptors needed, worst case */
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#define DESC_NEEDED (MAX_SKB_FRAGS + 6)
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#define I40E_MIN_DESC_PENDING 4
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#define I40E_TX_FLAGS_HW_VLAN BIT(1)
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#define I40E_TX_FLAGS_SW_VLAN BIT(2)
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#define I40E_TX_FLAGS_TSO BIT(3)
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#define I40E_TX_FLAGS_IPV4 BIT(4)
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#define I40E_TX_FLAGS_IPV6 BIT(5)
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#define I40E_TX_FLAGS_FCCRC BIT(6)
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#define I40E_TX_FLAGS_FSO BIT(7)
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#define I40E_TX_FLAGS_TSYN BIT(8)
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#define I40E_TX_FLAGS_FD_SB BIT(9)
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#define I40E_TX_FLAGS_UDP_TUNNEL BIT(10)
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@ -332,9 +310,7 @@ enum i40e_ring_state_t {
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/* some useful defines for virtchannel interface, which
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* is the only remaining user of header split
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*/
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#define I40E_RX_DTYPE_NO_SPLIT 0
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#define I40E_RX_DTYPE_HEADER_SPLIT 1
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#define I40E_RX_DTYPE_SPLIT_ALWAYS 2
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#define I40E_RX_SPLIT_L2 0x1
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#define I40E_RX_SPLIT_IP 0x2
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#define I40E_RX_SPLIT_TCP_UDP 0x4
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@ -444,7 +420,6 @@ static inline void set_ring_xdp(struct i40e_ring *ring)
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#define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e
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#define I40E_ITR_ADAPTIVE_LATENCY 0x8000
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#define I40E_ITR_ADAPTIVE_BULK 0x0000
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#define ITR_IS_BULK(x) (!((x) & I40E_ITR_ADAPTIVE_LATENCY))
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struct i40e_ring_container {
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struct i40e_ring *ring; /* pointer to linked list of ring(s) */
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@ -84,8 +84,6 @@ enum i40e_debug_mask {
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
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I40E_GLGEN_MSCA_OPCODE_SHIFT)
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@ -178,21 +176,9 @@ struct i40e_link_status {
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u8 module_type[3];
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/* 1st byte: module identifier */
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#define I40E_MODULE_TYPE_SFP 0x03
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#define I40E_MODULE_TYPE_QSFP 0x0D
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/* 2nd byte: ethernet compliance codes for 10/40G */
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#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
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#define I40E_MODULE_TYPE_40G_LR4 0x02
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#define I40E_MODULE_TYPE_40G_SR4 0x04
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#define I40E_MODULE_TYPE_40G_CR4 0x08
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#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
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#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
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#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
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#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
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/* 3rd byte: ethernet compliance codes for 1G */
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#define I40E_MODULE_TYPE_1000BASE_SX 0x01
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#define I40E_MODULE_TYPE_1000BASE_LX 0x02
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#define I40E_MODULE_TYPE_1000BASE_CX 0x04
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#define I40E_MODULE_TYPE_1000BASE_T 0x08
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};
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struct i40e_phy_info {
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@ -262,9 +248,6 @@ struct i40e_phy_info {
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/* Capabilities of a PF or a VF or the whole device */
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struct i40e_hw_capabilities {
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u32 switch_mode;
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#define I40E_NVM_IMAGE_TYPE_EVB 0x0
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#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
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#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
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/* Cloud filter modes:
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* Mode1: Filter on L4 port only
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@ -273,14 +256,10 @@ struct i40e_hw_capabilities {
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*/
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#define I40E_CLOUD_FILTER_MODE1 0x6
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#define I40E_CLOUD_FILTER_MODE2 0x7
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#define I40E_CLOUD_FILTER_MODE3 0x8
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#define I40E_SWITCH_MODE_MASK 0xF
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u32 management_mode;
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u32 mng_protocols_over_mctp;
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#define I40E_MNG_PROTOCOL_PLDM 0x2
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#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
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#define I40E_MNG_PROTOCOL_NCSI 0x8
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u32 npar_enable;
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u32 os2bmc;
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u32 valid_functions;
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@ -294,13 +273,8 @@ struct i40e_hw_capabilities {
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bool flex10_enable;
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bool flex10_capable;
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u32 flex10_mode;
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#define I40E_FLEX10_MODE_UNKNOWN 0x0
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#define I40E_FLEX10_MODE_DCC 0x1
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#define I40E_FLEX10_MODE_DCI 0x2
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u32 flex10_status;
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#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
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#define I40E_FLEX10_STATUS_VC_MODE 0x2
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bool sec_rev_disabled;
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bool update_disabled;
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@ -421,11 +395,8 @@ enum i40e_nvmupd_state {
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#define I40E_NVM_AQE 0xe
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#define I40E_NVM_EXEC 0xf
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#define I40E_NVM_ADAPT_SHIFT 16
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#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
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#define I40E_NVMUPD_MAX_DATA 4096
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#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
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struct i40e_nvm_access {
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u32 command;
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@ -438,7 +409,6 @@ struct i40e_nvm_access {
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/* (Q)SFP module access definitions */
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#define I40E_I2C_EEPROM_DEV_ADDR 0xA0
|
||||
#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
|
||||
#define I40E_MODULE_TYPE_ADDR 0x00
|
||||
#define I40E_MODULE_REVISION_ADDR 0x01
|
||||
#define I40E_MODULE_SFF_8472_COMP 0x5E
|
||||
#define I40E_MODULE_SFF_8472_SWAP 0x5C
|
||||
@ -547,7 +517,6 @@ struct i40e_dcbx_config {
|
||||
#define I40E_DCBX_MODE_CEE 0x1
|
||||
#define I40E_DCBX_MODE_IEEE 0x2
|
||||
u8 app_mode;
|
||||
#define I40E_DCBX_APPS_NON_WILLING 0x1
|
||||
u32 numapps;
|
||||
u32 tlv_status; /* CEE mode TLV status */
|
||||
struct i40e_dcb_ets_config etscfg;
|
||||
@ -895,9 +864,6 @@ enum i40e_rx_ptype_payload_layer {
|
||||
#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
|
||||
I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
|
||||
|
||||
#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
|
||||
#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
|
||||
I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
|
||||
|
||||
#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
|
||||
#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
|
||||
@ -926,7 +892,6 @@ enum i40e_rx_desc_pe_status_bits {
|
||||
I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
|
||||
};
|
||||
|
||||
#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
|
||||
#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
|
||||
|
||||
#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
|
||||
@ -963,8 +928,6 @@ struct i40e_tx_desc {
|
||||
__le64 cmd_type_offset_bsz;
|
||||
};
|
||||
|
||||
#define I40E_TXD_QW1_DTYPE_SHIFT 0
|
||||
#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
|
||||
|
||||
enum i40e_tx_desc_dtype_value {
|
||||
I40E_TX_DESC_DTYPE_DATA = 0x0,
|
||||
@ -980,7 +943,6 @@ enum i40e_tx_desc_dtype_value {
|
||||
};
|
||||
|
||||
#define I40E_TXD_QW1_CMD_SHIFT 4
|
||||
#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
|
||||
|
||||
enum i40e_tx_desc_cmd_bits {
|
||||
I40E_TX_DESC_CMD_EOP = 0x0001,
|
||||
@ -1004,8 +966,6 @@ enum i40e_tx_desc_cmd_bits {
|
||||
};
|
||||
|
||||
#define I40E_TXD_QW1_OFFSET_SHIFT 16
|
||||
#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
|
||||
I40E_TXD_QW1_OFFSET_SHIFT)
|
||||
|
||||
enum i40e_tx_desc_length_fields {
|
||||
/* Note: These are predefined bit offsets */
|
||||
@ -1015,11 +975,8 @@ enum i40e_tx_desc_length_fields {
|
||||
};
|
||||
|
||||
#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
|
||||
#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
|
||||
I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
|
||||
|
||||
#define I40E_TXD_QW1_L2TAG1_SHIFT 48
|
||||
#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
|
||||
|
||||
/* Context descriptors */
|
||||
struct i40e_tx_context_desc {
|
||||
@ -1029,11 +986,8 @@ struct i40e_tx_context_desc {
|
||||
__le64 type_cmd_tso_mss;
|
||||
};
|
||||
|
||||
#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
|
||||
#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
|
||||
#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
|
||||
|
||||
enum i40e_tx_ctx_desc_cmd_bits {
|
||||
I40E_TX_CTX_DESC_TSO = 0x01,
|
||||
@ -1048,19 +1002,10 @@ enum i40e_tx_ctx_desc_cmd_bits {
|
||||
};
|
||||
|
||||
#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
|
||||
#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
|
||||
I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
|
||||
#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
|
||||
I40E_TXD_CTX_QW1_MSS_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
|
||||
#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
|
||||
#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
|
||||
I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
|
||||
|
||||
enum i40e_tx_ctx_desc_eipt_offload {
|
||||
I40E_TX_CTX_EXT_IP_NONE = 0x0,
|
||||
@ -1070,28 +1015,16 @@ enum i40e_tx_ctx_desc_eipt_offload {
|
||||
};
|
||||
|
||||
#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
|
||||
#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
|
||||
I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
|
||||
#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
|
||||
#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
|
||||
#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
|
||||
BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
|
||||
|
||||
#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
|
||||
#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
|
||||
I40E_TXD_CTX_QW0_NATLEN_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
|
||||
#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
|
||||
I40E_TXD_CTX_QW0_DECTTL_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
|
||||
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
|
||||
@ -1161,11 +1094,8 @@ enum i40e_filter_program_desc_fd_status {
|
||||
I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
|
||||
#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
|
||||
I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
|
||||
|
||||
enum i40e_filter_program_desc_pcmd {
|
||||
I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
|
||||
@ -1316,7 +1246,6 @@ struct i40e_hw_port_stats {
|
||||
#define I40E_NVM_OEM_VER_OFF 0x83
|
||||
#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
|
||||
#define I40E_SR_NVM_WAKE_ON_LAN 0x19
|
||||
#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
|
||||
#define I40E_SR_NVM_EETRACK_LO 0x2D
|
||||
#define I40E_SR_NVM_EETRACK_HI 0x2E
|
||||
#define I40E_SR_VPD_PTR 0x2F
|
||||
@ -1329,7 +1258,6 @@ struct i40e_hw_port_stats {
|
||||
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
|
||||
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
|
||||
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
|
||||
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
|
||||
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
|
||||
#define I40E_PTR_TYPE BIT(15)
|
||||
#define I40E_SR_OCP_CFG_WORD0 0x2B
|
||||
@ -1463,14 +1391,11 @@ struct i40e_lldp_variables {
|
||||
/* Offsets into Alternate Ram */
|
||||
#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
|
||||
#define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
|
||||
#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
|
||||
#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
|
||||
#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
|
||||
#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
|
||||
|
||||
/* Alternate Ram Bandwidth Masks */
|
||||
#define I40E_ALT_BW_VALUE_MASK 0xFF
|
||||
#define I40E_ALT_BW_RELATIVE_MASK 0x40000000
|
||||
#define I40E_ALT_BW_VALID_MASK 0x80000000
|
||||
|
||||
/* RSS Hash Table Size */
|
||||
@ -1529,9 +1454,7 @@ struct i40e_package_header {
|
||||
/* Generic segment header */
|
||||
struct i40e_generic_seg_header {
|
||||
#define SEGMENT_TYPE_METADATA 0x00000001
|
||||
#define SEGMENT_TYPE_NOTES 0x00000002
|
||||
#define SEGMENT_TYPE_I40E 0x00000011
|
||||
#define SEGMENT_TYPE_X722 0x00000012
|
||||
u32 type;
|
||||
struct i40e_ddp_version version;
|
||||
u32 size;
|
||||
@ -1541,7 +1464,6 @@ struct i40e_generic_seg_header {
|
||||
struct i40e_metadata_segment {
|
||||
struct i40e_generic_seg_header header;
|
||||
struct i40e_ddp_version version;
|
||||
#define I40E_DDP_TRACKID_RDONLY 0
|
||||
#define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
|
||||
u32 track_id;
|
||||
char name[I40E_DDP_NAME_SIZE];
|
||||
@ -1575,10 +1497,6 @@ struct i40e_profile_section_header {
|
||||
#define SECTION_TYPE_AQ 0x00000801
|
||||
#define SECTION_TYPE_RB_AQ 0x00001801
|
||||
#define SECTION_TYPE_NOTE 0x80000000
|
||||
#define SECTION_TYPE_NAME 0x80000001
|
||||
#define SECTION_TYPE_PROTO 0x80000002
|
||||
#define SECTION_TYPE_PCTYPE 0x80000003
|
||||
#define SECTION_TYPE_PTYPE 0x80000004
|
||||
u32 type;
|
||||
u32 offset;
|
||||
u32 size;
|
||||
|
||||
@ -10,7 +10,6 @@
|
||||
|
||||
#define I40E_VIRTCHNL_SUPPORTED_QTYPES 2
|
||||
|
||||
#define I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED 3
|
||||
#define I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED 10
|
||||
|
||||
#define I40E_VLAN_PRIORITY_SHIFT 13
|
||||
|
||||
@ -37,11 +37,6 @@ enum i40e_client_instance_state {
|
||||
struct i40e_ops;
|
||||
struct i40e_client;
|
||||
|
||||
/* HW does not define a type value for AEQ; only for RX/TX and CEQ.
|
||||
* In order for us to keep the interface simple, SW will define a
|
||||
* unique type value for AEQ.
|
||||
*/
|
||||
#define I40E_QUEUE_TYPE_PE_AEQ 0x80
|
||||
#define I40E_QUEUE_INVALID_IDX 0xFFFF
|
||||
|
||||
struct i40e_qv_info {
|
||||
@ -56,7 +51,6 @@ struct i40e_qvlist_info {
|
||||
struct i40e_qv_info qv_info[1];
|
||||
};
|
||||
|
||||
#define I40E_CLIENT_MSIX_ALL 0xFFFFFFFF
|
||||
|
||||
/* set of LAN parameters useful for clients managed by LAN */
|
||||
|
||||
@ -87,7 +81,6 @@ struct i40e_info {
|
||||
u8 __iomem *hw_addr;
|
||||
u8 fid; /* function id, PF id or VF id */
|
||||
#define I40E_CLIENT_FTYPE_PF 0
|
||||
#define I40E_CLIENT_FTYPE_VF 1
|
||||
u8 ftype; /* function type, PF or VF */
|
||||
void *pf;
|
||||
|
||||
@ -184,8 +177,6 @@ struct i40e_client {
|
||||
unsigned long state; /* client state */
|
||||
atomic_t ref_cnt; /* Count of all the client devices of this kind */
|
||||
u32 flags;
|
||||
#define I40E_CLIENT_FLAGS_LAUNCH_ON_PROBE BIT(0)
|
||||
#define I40E_TX_FLAGS_NOTIFY_OTHER_EVENTS BIT(2)
|
||||
u8 type;
|
||||
#define I40E_CLIENT_IWARP 0
|
||||
const struct i40e_client_ops *ops; /* client ops provided by the client */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user