iwlwifi: allow to wait for a subset of the queues
This will be used later to flush / wait for queues that are related to a specific vif. Reviewed-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
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@ -180,7 +180,7 @@ void iwlagn_dev_txfifo_flush(struct iwl_priv *priv)
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goto done;
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}
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IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
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iwl_trans_wait_tx_queue_empty(priv->trans);
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iwl_trans_wait_tx_queue_empty(priv->trans, 0xffffffff);
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done:
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ieee80211_wake_queues(priv->hw);
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mutex_unlock(&priv->mutex);
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@ -1119,7 +1119,7 @@ static void iwlagn_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
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}
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}
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IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
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iwl_trans_wait_tx_queue_empty(priv->trans);
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iwl_trans_wait_tx_queue_empty(priv->trans, 0xffffffff);
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done:
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mutex_unlock(&priv->mutex);
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IWL_DEBUG_MAC80211(priv, "leave\n");
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@ -437,8 +437,7 @@ struct iwl_trans;
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* this one. The op_mode must not configure the HCMD queue. May sleep.
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* @txq_disable: de-configure a Tx queue to send AMPDUs
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* Must be atomic
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* @wait_tx_queue_empty: wait until all tx queues are empty
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* May sleep
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* @wait_tx_queue_empty: wait until tx queues are empty. May sleep.
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* @dbgfs_register: add the dbgfs files under this directory. Files will be
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* automatically deleted.
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* @write8: write a u8 to a register at offset ofs from the BAR
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@ -490,7 +489,7 @@ struct iwl_trans_ops {
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void (*txq_disable)(struct iwl_trans *trans, int queue);
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int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir);
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int (*wait_tx_queue_empty)(struct iwl_trans *trans);
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int (*wait_tx_queue_empty)(struct iwl_trans *trans, u32 txq_bm);
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void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
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void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
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@ -759,12 +758,13 @@ static inline void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue,
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IWL_MAX_TID_COUNT, IWL_FRAME_LIMIT, 0);
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}
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static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans)
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static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans,
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u32 txq_bm)
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{
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if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
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IWL_ERR(trans, "%s bad state = %d", __func__, trans->state);
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return trans->ops->wait_tx_queue_empty(trans);
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return trans->ops->wait_tx_queue_empty(trans, txq_bm);
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}
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static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans,
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@ -1257,7 +1257,7 @@ static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
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#define IWL_FLUSH_WAIT_MS 2000
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static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq;
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@ -1272,6 +1272,10 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
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if (cnt == trans_pcie->cmd_queue)
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continue;
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if (!test_bit(cnt, trans_pcie->queue_used))
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continue;
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if (!(BIT(cnt) & txq_bm))
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continue;
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txq = &trans_pcie->txq[cnt];
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q = &txq->q;
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while (q->read_ptr != q->write_ptr && !time_after(jiffies,
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