Revert "drm/i915/dp: use VBT provided eDP params if available"
This reverts commit 869184a675.
This is required for the Sony Vaio Jesse was working on at the time, but
breaks most other eDP machines - machines that were working in earlier
kernels.
Reported-and-tested-by: Dave Airlie <airlied@redhat.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31188
Tested-by: Zhao Jian <jian.j.zhao@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
c5d1b51d35
commit
3cf2efb1a7
@ -584,17 +584,6 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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mode->clock = dev_priv->panel_fixed_mode->clock;
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}
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/* Just use VBT values for eDP */
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if (is_edp(intel_dp)) {
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intel_dp->lane_count = dev_priv->edp.lanes;
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intel_dp->link_bw = dev_priv->edp.rate;
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adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
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DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",
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intel_dp->link_bw, intel_dp->lane_count,
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adjusted_mode->clock);
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return true;
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}
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for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
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for (clock = 0; clock <= max_clock; clock++) {
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int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
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@ -613,6 +602,19 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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}
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}
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if (is_edp(intel_dp)) {
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/* okay we failed just pick the highest */
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intel_dp->lane_count = max_lane_count;
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intel_dp->link_bw = bws[max_clock];
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adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
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DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
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"count %d clock %d\n",
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intel_dp->link_bw, intel_dp->lane_count,
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adjusted_mode->clock);
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return true;
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}
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return false;
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}
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@ -1087,21 +1089,11 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
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}
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static uint32_t
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intel_dp_signal_levels(struct intel_dp *intel_dp)
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intel_dp_signal_levels(uint8_t train_set, int lane_count)
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{
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struct drm_device *dev = intel_dp->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t signal_levels = 0;
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u8 train_set = intel_dp->train_set[0];
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u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;
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u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;
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uint32_t signal_levels = 0;
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if (is_edp(intel_dp)) {
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vswing = dev_priv->edp.vswing;
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preemphasis = dev_priv->edp.preemphasis;
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}
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switch (vswing) {
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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default:
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signal_levels |= DP_VOLTAGE_0_4;
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@ -1116,7 +1108,7 @@ intel_dp_signal_levels(struct intel_dp *intel_dp)
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signal_levels |= DP_VOLTAGE_1_2;
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break;
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}
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switch (preemphasis) {
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switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
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case DP_TRAIN_PRE_EMPHASIS_0:
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default:
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signal_levels |= DP_PRE_EMPHASIS_0;
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@ -1202,18 +1194,6 @@ intel_channel_eq_ok(struct intel_dp *intel_dp)
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return true;
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}
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static bool
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intel_dp_aux_handshake_required(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (is_edp(intel_dp) && dev_priv->no_aux_handshake)
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return false;
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return true;
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}
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static bool
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intel_dp_set_link_train(struct intel_dp *intel_dp,
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uint32_t dp_reg_value,
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@ -1226,9 +1206,6 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
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I915_WRITE(intel_dp->output_reg, dp_reg_value);
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POSTING_READ(intel_dp->output_reg);
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if (!intel_dp_aux_handshake_required(intel_dp))
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return true;
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intel_dp_aux_native_write_1(intel_dp,
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DP_TRAINING_PATTERN_SET,
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dp_train_pat);
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@ -1261,11 +1238,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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POSTING_READ(intel_dp->output_reg);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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if (intel_dp_aux_handshake_required(intel_dp))
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
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intel_dp->link_configuration,
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DP_LINK_CONFIGURATION_SIZE);
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
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intel_dp->link_configuration,
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DP_LINK_CONFIGURATION_SIZE);
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DP |= DP_PORT_EN;
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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@ -1283,7 +1259,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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signal_levels = intel_dp_signal_levels(intel_dp);
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signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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@ -1297,37 +1273,33 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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break;
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/* Set training pattern 1 */
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udelay(500);
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if (intel_dp_aux_handshake_required(intel_dp)) {
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udelay(100);
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if (!intel_dp_get_link_status(intel_dp))
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break;
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} else {
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if (!intel_dp_get_link_status(intel_dp))
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break;
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if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
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clock_recovery = true;
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break;
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}
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/* Check to see if we've tried the max voltage */
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for (i = 0; i < intel_dp->lane_count; i++)
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if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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break;
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if (i == intel_dp->lane_count)
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break;
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/* Check to see if we've tried the same voltage 5 times */
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if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
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++tries;
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if (tries == 5)
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break;
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} else
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tries = 0;
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voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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/* Compute new intel_dp->train_set as requested by target */
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intel_get_adjust_train(intel_dp);
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if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
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clock_recovery = true;
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break;
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}
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/* Check to see if we've tried the max voltage */
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for (i = 0; i < intel_dp->lane_count; i++)
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if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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break;
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if (i == intel_dp->lane_count)
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break;
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/* Check to see if we've tried the same voltage 5 times */
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if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
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++tries;
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if (tries == 5)
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break;
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} else
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tries = 0;
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voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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/* Compute new intel_dp->train_set as requested by target */
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intel_get_adjust_train(intel_dp);
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}
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intel_dp->DP = DP;
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@ -1354,7 +1326,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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signal_levels = intel_dp_signal_levels(intel_dp);
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signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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@ -1368,28 +1340,24 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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DP_TRAINING_PATTERN_2))
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break;
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udelay(500);
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if (!intel_dp_aux_handshake_required(intel_dp)) {
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udelay(400);
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if (!intel_dp_get_link_status(intel_dp))
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break;
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} else {
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if (!intel_dp_get_link_status(intel_dp))
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break;
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if (intel_channel_eq_ok(intel_dp)) {
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channel_eq = true;
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break;
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}
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/* Try 5 times */
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if (tries > 5)
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break;
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/* Compute new intel_dp->train_set as requested by target */
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intel_get_adjust_train(intel_dp);
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++tries;
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if (intel_channel_eq_ok(intel_dp)) {
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channel_eq = true;
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break;
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}
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/* Try 5 times */
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if (tries > 5)
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break;
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/* Compute new intel_dp->train_set as requested by target */
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intel_get_adjust_train(intel_dp);
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++tries;
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}
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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reg = DP | DP_LINK_TRAIN_OFF_CPT;
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else
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