ASoC: Intel: catpt: Cleanup after power routines streamlining
With LPT switching to WPT-based power on/off routines, functions that have been previously used by it are rendered redundant so remove them. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Link: https://lore.kernel.org/r/20201116133332.8530-6-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -83,8 +83,6 @@ struct catpt_spec {
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u32 d3srampgd_bit;
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u32 d3pgd_bit;
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void (*pll_shutdown)(struct catpt_dev *cdev, bool enable);
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int (*power_up)(struct catpt_dev *cdev);
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int (*power_down)(struct catpt_dev *cdev);
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};
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struct catpt_dev {
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@ -128,8 +126,6 @@ int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan,
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void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable);
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void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable);
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int lpt_dsp_power_up(struct catpt_dev *cdev);
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int lpt_dsp_power_down(struct catpt_dev *cdev);
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int catpt_dsp_power_up(struct catpt_dev *cdev);
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int catpt_dsp_power_down(struct catpt_dev *cdev);
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int catpt_dsp_stall(struct catpt_dev *cdev, bool stall);
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@ -341,52 +341,6 @@ static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev)
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}
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}
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int lpt_dsp_power_down(struct catpt_dev *cdev)
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{
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catpt_dsp_reset(cdev, true);
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/* set 24Mhz clock for both SSPs */
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catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
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CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
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catpt_dsp_select_lpclock(cdev, true, false);
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/* DRAM power gating all */
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catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask,
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cdev->spec->dram_mask);
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catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask,
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cdev->spec->iram_mask);
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catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);
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/* give hw time to drop off */
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udelay(50);
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return 0;
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}
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int lpt_dsp_power_up(struct catpt_dev *cdev)
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{
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/* SRAM power gating none */
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catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0);
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catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0);
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catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0);
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/* give hw time to wake up */
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udelay(100);
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catpt_dsp_select_lpclock(cdev, false, false);
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catpt_updatel_shim(cdev, CS1,
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CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1),
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CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1));
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/* stagger DSP reset after clock selection */
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udelay(50);
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catpt_dsp_reset(cdev, false);
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/* generate int deassert msg to fix inversed int logic */
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catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0);
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return 0;
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}
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int catpt_dsp_power_down(struct catpt_dev *cdev)
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{
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u32 mask, val;
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