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staging: rtl8192e: Join constants AGCTAB_ArrayLength with ..LengthPciE

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Join constants AGCTAB_ArrayLength with AGCTAB_ArrayLengthPciE to
RTL8192E_AGCTAB_ARR_LEN to improve readability.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/98a7553403ef95609fbcb84e4cc653628b96c56c.1678814935.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann 2023-03-14 19:42:56 +01:00 committed by Greg Kroah-Hartman
parent f933c226ce
commit 3dcf9a25d8
4 changed files with 4 additions and 5 deletions
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2
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
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@ -312,7 +312,7 @@ static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
struct r8192_priv *priv = rtllib_priv(dev);
AGCTAB_ArrayLen = AGCTAB_ArrayLength;
AGCTAB_ArrayLen = RTL8192E_AGCTAB_ARR_LEN;
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
if (priv->rf_type == RF_1T2R) {
PHY_REGArrayLen = PHY_REG_1T2RArrayLength;

1
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
View File

@ -9,7 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
#define RadioA_ArrayLength RadioA_ArrayLengthPciE
#define RadioB_ArrayLength RadioB_ArrayLengthPciE

2
drivers/staging/rtl8192e/rtl8192e/table.c
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@ -347,7 +347,7 @@ u32 Rtl8192PciEMACPHY_Array_PG[] = {
0x318, 0x00000fff, 0x00000800,
};
u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] = {
u32 Rtl8192PciEAGCTAB_Array[RTL8192E_AGCTAB_ARR_LEN] = {
0xc78, 0x7d000001,
0xc78, 0x7d010001,
0xc78, 0x7d020001,

4
drivers/staging/rtl8192e/rtl8192e/table.h
View File

@ -21,7 +21,7 @@ extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE];
extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE];
#define MACPHY_Array_PGLengthPciE 30
extern u32 Rtl8192PciEMACPHY_Array_PG[MACPHY_Array_PGLengthPciE];
#define AGCTAB_ArrayLengthPciE 384
extern u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE];
#define RTL8192E_AGCTAB_ARR_LEN 384
extern u32 Rtl8192PciEAGCTAB_Array[RTL8192E_AGCTAB_ARR_LEN];
#endif