drm/amd/pm: add callback to get bootup values for yellow carp
Add get_vbios_bootup_values function to get the bootup values for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaomeng Hou
Alex Deucher
parent
4b16196752
commit
3df43e65e7
@ -46,6 +46,8 @@ int smu_v13_0_1_check_fw_version(struct smu_context *smu);
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int smu_v13_0_1_fini_smc_tables(struct smu_context *smu);
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int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu);
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int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu);
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int smu_v13_0_1_set_driver_table_location(struct smu_context *smu);
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@ -29,6 +29,10 @@
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#include "smu_v13_0_1.h"
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#include "soc15_common.h"
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#include "smu_cmn.h"
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#include "atomfirmware.h"
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#include "amdgpu_atomfirmware.h"
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#include "amdgpu_atombios.h"
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#include "atom.h"
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#include "asic_reg/mp/mp_13_0_1_offset.h"
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#include "asic_reg/mp/mp_13_0_1_sh_mask.h"
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@ -122,6 +126,138 @@ int smu_v13_0_1_fini_smc_tables(struct smu_context *smu)
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return 0;
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}
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static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev,
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uint8_t clk_id,
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uint8_t syspll_id,
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uint32_t *clk_freq)
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{
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struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
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struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
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int ret, index;
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input.clk_id = clk_id;
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input.syspll_id = syspll_id;
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input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
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index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
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getsmuclockinfo);
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ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
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(uint32_t *)&input);
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if (ret)
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return -EINVAL;
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output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
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*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
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return 0;
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}
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int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu)
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{
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int ret, index;
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uint16_t size;
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uint8_t frev, crev;
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struct atom_common_table_header *header;
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struct atom_firmware_info_v3_4 *v_3_4;
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struct atom_firmware_info_v3_3 *v_3_3;
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struct atom_firmware_info_v3_1 *v_3_1;
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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firmwareinfo);
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ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
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(uint8_t **)&header);
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if (ret)
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return ret;
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if (header->format_revision != 3) {
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dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
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return -EINVAL;
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}
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switch (header->content_revision) {
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case 0:
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case 1:
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case 2:
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v_3_1 = (struct atom_firmware_info_v3_1 *)header;
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smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
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smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
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smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
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smu->smu_table.boot_values.socclk = 0;
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smu->smu_table.boot_values.dcefclk = 0;
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smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
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smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
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smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
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smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
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smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
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break;
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case 3:
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v_3_3 = (struct atom_firmware_info_v3_3 *)header;
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smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
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smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
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smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
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smu->smu_table.boot_values.socclk = 0;
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smu->smu_table.boot_values.dcefclk = 0;
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smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
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smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
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smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
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smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
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smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
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break;
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case 4:
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default:
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v_3_4 = (struct atom_firmware_info_v3_4 *)header;
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smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
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smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
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smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
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smu->smu_table.boot_values.socclk = 0;
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smu->smu_table.boot_values.dcefclk = 0;
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smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
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smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
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smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
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smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
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smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
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break;
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}
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smu->smu_table.boot_values.format_revision = header->format_revision;
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smu->smu_table.boot_values.content_revision = header->content_revision;
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
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(uint8_t)0,
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&smu->smu_table.boot_values.socclk);
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
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(uint8_t)0,
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&smu->smu_table.boot_values.dcefclk);
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL0_ECLK_ID,
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(uint8_t)0,
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&smu->smu_table.boot_values.eclk);
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL0_VCLK_ID,
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(uint8_t)0,
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&smu->smu_table.boot_values.vclk);
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL0_DCLK_ID,
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(uint8_t)0,
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&smu->smu_table.boot_values.dclk);
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if ((smu->smu_table.boot_values.format_revision == 3) &&
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(smu->smu_table.boot_values.content_revision >= 2))
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smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
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(uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
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(uint8_t)SMU11_SYSPLL1_2_ID,
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&smu->smu_table.boot_values.fclk);
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return 0;
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}
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int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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@ -820,6 +820,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {
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.check_fw_version = smu_v13_0_1_check_fw_version,
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.init_smc_tables = yellow_carp_init_smc_tables,
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.fini_smc_tables = smu_v13_0_1_fini_smc_tables,
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.get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values,
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.system_features_control = yellow_carp_system_features_control,
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.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
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.send_smc_msg = smu_cmn_send_smc_msg,
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