Drop legacy data for dra7 and omap4/5 for genpd support for v5.13
Similar to what we have already done for am3 and 4, we can now boot dra7, omap4, and omap5 with devicetree data and genpd without legacy SoC specific built-in data. Let's drop the legacy data for these SoCs, and the related "ti,hwmods" custom devicetree property. As with these changes we now expect to have complete devicetree data, let's also warn in the case if an old devicetree data is noticed. And with the warning provided, there should not be any need to delay dropping the legacy data as it just unnecessarily complicates things. The main reasons for dropping the legacy data is to avoid the burden of maintaining a mixed boot process where both legacy built-in data and devicetree data are needed. And we can now use standard reset driver, genpd, and simple-pm-bus features. These patches are based on the related devicetree changes to add the missing interconnect target module configuration for these SoCs. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmBhhOERHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXO6JBAA311Vob76DmZCVEh3ho/NtwszUTHAuzNM nGJYMrFCpHOFRb7d7I6Wp4ke8Z7IHuHKYhgWikEgs0f2KdCNlpDMwgtEIB1+1MNO foyjJ5v35v+w0aW+/zqeLMWMWAOxqNga142jb2l7paO6AwfrT8qhh7olMdTvustu 7oUfh2Zl8rgs31tygLF2pizZf+JEfaZYlWDor4CfO/7M7/mdcG7cts19PI8FV21E MBhIvEJHmheZIj9R7sJpeVkbgP0qwR7nVXEDREuET/2huj1Q5bSH8JKVJTGOGiOU 4O1ZJbghl2kVQycvzYY2rjV8KTnQknsxQShsccDyreaV/6jsq5XtRak8bFNvN3kw YEBFI5YIPt+VyK1aWEY6BtFsGBkt6gc6la3ehnFoL64qdbcWIyVJ/DgNWs7t82/z POZMQUkdpB75a+9IfY8pGv4hJjdJWvQEErW/y+DR0OPqb2izspvM/hz0g3QtstAi +9CrkxIE2Nh6aBc/WFnH+QeX0HvkMyrPYBRAPode/dmBgY6chYHHV2M6oRiWhrJb 00hkqBhJ5Mf55dQ8Dh2mNJtelJl59JlQRiywWecvVW0PwncquMaHlruGmwbSyRAu j1kwmsYhH/+4DeDKNCA2JqluoXVUe77YgnmOz97B930/sRrif/82WChiSe7Ypplq uDu5XVCSo3A= =0CZ2 -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.13/genpd-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc Drop legacy data for dra7 and omap4/5 for genpd support for v5.13 Similar to what we have already done for am3 and 4, we can now boot dra7, omap4, and omap5 with devicetree data and genpd without legacy SoC specific built-in data. Let's drop the legacy data for these SoCs, and the related "ti,hwmods" custom devicetree property. As with these changes we now expect to have complete devicetree data, let's also warn in the case if an old devicetree data is noticed. And with the warning provided, there should not be any need to delay dropping the legacy data as it just unnecessarily complicates things. The main reasons for dropping the legacy data is to avoid the burden of maintaining a mixed boot process where both legacy built-in data and devicetree data are needed. And we can now use standard reset driver, genpd, and simple-pm-bus features. These patches are based on the related devicetree changes to add the missing interconnect target module configuration for these SoCs. * tag 'omap-for-v5.13/genpd-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (87 commits) bus: ti-sysc: Warn about old dtb for dra7 and omap4/5 ARM: OMAP2+: Stop building legacy code for dra7 and omap4/5 ARM: OMAP2+: Drop legacy platform data for omap5 hwmod ARM: OMAP2+: Drop legacy platform data for omap5 l3 ARM: OMAP2+: Drop legacy platform data for omap5 l4_cfg ARM: OMAP2+: Drop legacy platform data for omap5 l4_per ARM: OMAP2+: Drop legacy platform data for omap5 l4_wkup ARM: OMAP2+: Drop legacy platform data for omap5 sata ARM: OMAP2+: Drop legacy platform data for omap5 mpu ARM: OMAP2+: Drop legacy platform data for omap5 emif ARM: OMAP2+: Drop legacy platform data for omap5 dmm ARM: dts: Configure simple-pm-bus for omap5 l3 ARM: dts: Configure simple-pm-bus for omap5 l4_cfg ARM: dts: Configure simple-pm-bus for omap5 l4_per ARM: dts: Configure simple-pm-bus for omap5 l4_wkup ARM: dts: Move omap5 l3-noc to a separate node ARM: dts: Move omap5 mmio-sram out of l3 interconnect ARM: dts: Configure interconnect target module for omap5 sata ARM: dts: Configure interconnect target module for omap5 gpmc ARM: dts: Configure interconnect target module for omap5 mpu ... Link: https://lore.kernel.org/r/pull-1617004205-537424@atomide.com-3 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
3e26eccd40
@ -40,6 +40,9 @@
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ethernet1 = &cpsw_emac1;
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spi0 = &spi0;
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spi1 = &spi1;
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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};
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cpus {
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@ -1,5 +1,8 @@
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&l4_cfg { /* 0x4a000000 */
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compatible = "ti,dra7-l4-cfg", "simple-bus";
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compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
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power-domains = <&prm_coreaon>;
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clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x4a000000 0x800>,
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<0x4a000800 0x800>,
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<0x4a001000 0x1000>;
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@ -11,7 +14,7 @@
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<0x00200000 0x4a200000 0x100000>; /* segment 2 */
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segment@0 { /* 0x4a000000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@ -493,7 +496,7 @@
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};
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segment@100000 { /* 0x4a100000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
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@ -572,11 +575,33 @@
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};
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target-module@40000 { /* 0x4a140000, ap 31 06.0 */
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compatible = "ti,sysc";
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status = "disabled";
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#address-cells = <1>;
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x400fc 4>,
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<0x41100 4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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power-domains = <&prm_l3init>;
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clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
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clock-names = "fck";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x0 0x40000 0x10000>;
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sata: sata@0 {
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compatible = "snps,dwc-ahci";
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reg = <0 0x1100>, <0x1100 0x8>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
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ports-implemented = <0x1>;
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};
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};
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target-module@51000 { /* 0x4a151000, ap 33 50.0 */
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@ -789,7 +814,7 @@
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};
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segment@200000 { /* 0x4a200000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
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@ -1006,7 +1031,10 @@
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};
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&l4_per1 { /* 0x48000000 */
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compatible = "ti,dra7-l4-per1", "simple-bus";
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compatible = "ti,dra7-l4-per1", "simple-pm-bus";
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power-domains = <&prm_l4per>;
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clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x48000000 0x800>,
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<0x48000800 0x800>,
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<0x48001000 0x400>,
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@ -1020,7 +1048,7 @@
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<0x00200000 0x48200000 0x200000>; /* segment 1 */
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segment@0 { /* 0x48000000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@ -2269,14 +2297,17 @@
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};
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segment@200000 { /* 0x48200000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&l4_per2 { /* 0x48400000 */
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compatible = "ti,dra7-l4-per2", "simple-bus";
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compatible = "ti,dra7-l4-per2", "simple-pm-bus";
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power-domains = <&prm_l4per>;
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clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x48400000 0x800>,
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<0x48400800 0x800>,
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<0x48401000 0x400>,
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@ -2296,7 +2327,7 @@
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<0x48454000 0x48454000 0x400000>; /* L3 data port */
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segment@0 { /* 0x48400000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@ -3094,7 +3125,10 @@
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};
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&l4_per3 { /* 0x48800000 */
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compatible = "ti,dra7-l4-per3", "simple-bus";
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compatible = "ti,dra7-l4-per3", "simple-pm-bus";
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power-domains = <&prm_l4per>;
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clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x48800000 0x800>,
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<0x48800800 0x800>,
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<0x48801000 0x400>,
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@ -3106,7 +3140,7 @@
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ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
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segment@0 { /* 0x48800000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@ -4205,7 +4239,10 @@
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};
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&l4_wkup { /* 0x4ae00000 */
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compatible = "ti,dra7-l4-wkup", "simple-bus";
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compatible = "ti,dra7-l4-wkup", "simple-pm-bus";
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power-domains = <&prm_wkupaon>;
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clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x4ae00000 0x800>,
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<0x4ae00800 0x800>,
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<0x4ae01000 0x1000>;
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@ -4218,7 +4255,7 @@
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<0x00030000 0x4ae30000 0x010000>; /* segment 3 */
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segment@0 { /* 0x4ae00000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@ -4295,7 +4332,7 @@
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};
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segment@10000 { /* 0x4ae10000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
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@ -4405,7 +4442,7 @@
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};
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segment@20000 { /* 0x4ae20000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
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@ -4511,7 +4548,7 @@
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};
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segment@30000 { /* 0x4ae30000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
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@ -124,18 +124,6 @@
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};
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the SOC interconnect.
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* The real OMAP interconnect network is quite complex.
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@ -144,16 +132,22 @@
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* hierarchy.
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*/
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ocp: ocp {
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compatible = "ti,dra7-l3-noc", "simple-bus";
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compatible = "simple-pm-bus";
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power-domains = <&prm_core>;
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clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
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<&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0xc0000000>;
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dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
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ti,hwmods = "l3_main_1", "l3_main_2";
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reg = <0x0 0x44000000 0x0 0x1000000>,
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<0x0 0x45000000 0x0 0x1000>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l3-noc@44000000 {
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compatible = "ti,dra7-l3-noc";
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reg = <0x44000000 0x1000>,
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<0x45000000 0x1000>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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l4_cfg: interconnect@4a000000 {
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};
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@ -161,36 +155,65 @@
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};
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l4_per1: interconnect@48000000 {
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};
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target-module@48210000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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power-domains = <&prm_mpu>;
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clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48210000 0x1f0000>;
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mpu {
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compatible = "ti,omap5-mpu";
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};
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};
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l4_per2: interconnect@48400000 {
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};
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l4_per3: interconnect@48800000 {
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};
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axi@0 {
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compatible = "simple-bus";
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/*
|
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* Register access seems to have complex dependencies and also
|
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* seems to need an enabled phy. See the TRM chapter for "Table
|
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* 26-678. Main Sequence PCIe Controller Global Initialization"
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* and also dra7xx_pcie_probe().
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*/
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axi0: target-module@51000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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power-domains = <&prm_l3init>;
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resets = <&prm_l3init 0>;
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reset-names = "rstctrl";
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clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
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<&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
|
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<&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
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clock-names = "fck", "phy-clk", "phy-clk-div";
|
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#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges = <0x51000000 0x51000000 0x3000
|
||||
0x0 0x20000000 0x10000000>;
|
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ranges = <0x51000000 0x51000000 0x3000>,
|
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<0x20000000 0x20000000 0x10000000>;
|
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dma-ranges;
|
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/**
|
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* To enable PCI endpoint mode, disable the pcie1_rc
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* node and enable pcie1_ep mode.
|
||||
*/
|
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pcie1_rc: pcie@51000000 {
|
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
|
||||
reg = <0x51000000 0x2000>,
|
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<0x51002000 0x14c>,
|
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<0x20001000 0x2000>;
|
||||
reg-names = "rc_dbics", "ti_conf", "config";
|
||||
interrupts = <0 232 0x4>, <0 233 0x4>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x03000 0 0x00010000
|
||||
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
|
||||
ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
|
||||
<0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
linux,pci-domain = <0>;
|
||||
ti,hwmods = "pcie1";
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pcie-phy0";
|
||||
ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
|
||||
@ -209,13 +232,15 @@
|
||||
};
|
||||
|
||||
pcie1_ep: pcie_ep@51000000 {
|
||||
reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
|
||||
reg = <0x51000000 0x28>,
|
||||
<0x51002000 0x14c>,
|
||||
<0x51001000 0x28>,
|
||||
<0x20001000 0x10000000>;
|
||||
reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
|
||||
interrupts = <0 232 0x4>;
|
||||
num-lanes = <1>;
|
||||
num-ib-windows = <4>;
|
||||
num-ob-windows = <16>;
|
||||
ti,hwmods = "pcie1";
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pcie-phy0";
|
||||
ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
|
||||
@ -224,28 +249,42 @@
|
||||
};
|
||||
};
|
||||
|
||||
axi@1 {
|
||||
compatible = "simple-bus";
|
||||
/*
|
||||
* Register access seems to have complex dependencies and also
|
||||
* seems to need an enabled phy. See the TRM chapter for "Table
|
||||
* 26-678. Main Sequence PCIe Controller Global Initialization"
|
||||
* and also dra7xx_pcie_probe().
|
||||
*/
|
||||
axi1: target-module@51800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
|
||||
<&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
|
||||
<&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
|
||||
clock-names = "fck", "phy-clk", "phy-clk-div";
|
||||
power-domains = <&prm_l3init>;
|
||||
resets = <&prm_l3init 1>;
|
||||
reset-names = "rstctrl";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges = <0x51800000 0x51800000 0x3000
|
||||
0x0 0x30000000 0x10000000>;
|
||||
ranges = <0x51800000 0x51800000 0x3000>,
|
||||
<0x30000000 0x30000000 0x10000000>;
|
||||
dma-ranges;
|
||||
status = "disabled";
|
||||
pcie2_rc: pcie@51800000 {
|
||||
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
|
||||
reg = <0x51800000 0x2000>,
|
||||
<0x51802000 0x14c>,
|
||||
<0x30001000 0x2000>;
|
||||
reg-names = "rc_dbics", "ti_conf", "config";
|
||||
interrupts = <0 355 0x4>, <0 356 0x4>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x03000 0 0x00010000
|
||||
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
|
||||
ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
|
||||
<0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
linux,pci-domain = <1>;
|
||||
ti,hwmods = "pcie2";
|
||||
phys = <&pcie2_phy>;
|
||||
phy-names = "pcie-phy0";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
@ -336,8 +375,15 @@
|
||||
|
||||
target-module@43300000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43300000 0x4>;
|
||||
reg-names = "rev";
|
||||
reg = <0x43300000 0x4>,
|
||||
<0x43300010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
@ -369,8 +415,15 @@
|
||||
|
||||
target-module@43400000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43400000 0x4>;
|
||||
reg-names = "rev";
|
||||
reg = <0x43400000 0x4>,
|
||||
<0x43400010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
@ -387,8 +440,15 @@
|
||||
|
||||
target-module@43500000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43500000 0x4>;
|
||||
reg-names = "rev";
|
||||
reg = <0x43500000 0x4>,
|
||||
<0x43500010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
@ -403,11 +463,23 @@
|
||||
};
|
||||
};
|
||||
|
||||
dmm@4e000000 {
|
||||
compatible = "ti,omap5-dmm";
|
||||
reg = <0x4e000000 0x800>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "dmm";
|
||||
target-module@4e000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x4e000000 0x4>,
|
||||
<0x4e000010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ranges = <0x0 0x4e000000 0x2000000>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
dmm@0 {
|
||||
compatible = "ti,omap5-dmm";
|
||||
reg = <0 0x800>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu1: ipu@58820000 {
|
||||
@ -694,32 +766,36 @@
|
||||
>;
|
||||
};
|
||||
|
||||
qspi: spi@4b300000 {
|
||||
compatible = "ti,dra7xxx-qspi";
|
||||
reg = <0x4b300000 0x100>,
|
||||
<0x5c000000 0x4000000>;
|
||||
reg-names = "qspi_base", "qspi_mmap";
|
||||
syscon-chipselects = <&scm_conf 0x558>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "qspi";
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
|
||||
target-module@4b300000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x4b300000 0x4>,
|
||||
<0x4b300010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
num-cs = <4>;
|
||||
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4b300000 0x1000>,
|
||||
<0x5c000000 0x5c000000 0x4000000>;
|
||||
|
||||
/* OCP2SCP3 */
|
||||
sata: sata@4a141100 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
|
||||
ti,hwmods = "sata";
|
||||
ports-implemented = <0x1>;
|
||||
qspi: spi@0 {
|
||||
compatible = "ti,dra7xxx-qspi";
|
||||
reg = <0 0x100>,
|
||||
<0x5c000000 0x4000000>;
|
||||
reg-names = "qspi_base", "qspi_mmap";
|
||||
syscon-chipselects = <&scm_conf 0x558>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
|
||||
clock-names = "fck";
|
||||
num-cs = <4>;
|
||||
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* OCP2SCP1 */
|
||||
|
||||
@ -1,6 +1,9 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
&l4_cfg { /* 0x4a000000 */
|
||||
compatible = "ti,omap4-l4-cfg", "simple-bus";
|
||||
compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
|
||||
power-domains = <&prm_core>;
|
||||
clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x4a000000 0x800>,
|
||||
<0x4a000800 0x800>,
|
||||
<0x4a001000 0x1000>;
|
||||
@ -16,7 +19,7 @@
|
||||
<0x00300000 0x4a300000 0x080000>; /* segment 6 */
|
||||
|
||||
segment@0 { /* 0x4a000000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -43,7 +46,6 @@
|
||||
|
||||
target-module@2000 { /* 0x4a002000, ap 3 06.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
ti,hwmods = "ctrl_module_core";
|
||||
reg = <0x2000 0x4>,
|
||||
<0x2010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
@ -347,7 +349,7 @@
|
||||
};
|
||||
|
||||
segment@80000 { /* 0x4a080000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
|
||||
@ -639,7 +641,7 @@
|
||||
};
|
||||
|
||||
segment@100000 { /* 0x4a100000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
|
||||
@ -653,7 +655,6 @@
|
||||
|
||||
target-module@0 { /* 0x4a100000, ap 21 2a.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
ti,hwmods = "ctrl_module_pad_core";
|
||||
reg = <0x0 0x4>,
|
||||
<0x10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
@ -741,13 +742,13 @@
|
||||
};
|
||||
|
||||
segment@180000 { /* 0x4a180000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
segment@200000 { /* 0x4a200000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
|
||||
@ -903,13 +904,13 @@
|
||||
};
|
||||
|
||||
segment@280000 { /* 0x4a280000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
|
||||
@ -944,7 +945,10 @@
|
||||
};
|
||||
|
||||
&l4_wkup { /* 0x4a300000 */
|
||||
compatible = "ti,omap4-l4-wkup", "simple-bus";
|
||||
compatible = "ti,omap4-l4-wkup", "simple-pm-bus";
|
||||
power-domains = <&prm_wkup>;
|
||||
clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x4a300000 0x800>,
|
||||
<0x4a300800 0x800>,
|
||||
<0x4a301000 0x1000>;
|
||||
@ -956,7 +960,7 @@
|
||||
<0x00020000 0x4a320000 0x010000>; /* segment 2 */
|
||||
|
||||
segment@0 { /* 0x4a300000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -1041,7 +1045,6 @@
|
||||
|
||||
target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
ti,hwmods = "ctrl_module_wkup";
|
||||
reg = <0xc000 0x4>,
|
||||
<0xc010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
@ -1062,7 +1065,7 @@
|
||||
};
|
||||
|
||||
segment@10000 { /* 0x4a310000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
|
||||
@ -1202,7 +1205,6 @@
|
||||
|
||||
target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
ti,hwmods = "ctrl_module_pad_wkup";
|
||||
reg = <0xe000 0x4>,
|
||||
<0xe010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
@ -1231,7 +1233,7 @@
|
||||
};
|
||||
|
||||
segment@20000 { /* 0x4a320000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
|
||||
@ -1284,7 +1286,10 @@
|
||||
};
|
||||
|
||||
&l4_per { /* 0x48000000 */
|
||||
compatible = "ti,omap4-l4-per", "simple-bus";
|
||||
compatible = "ti,omap4-l4-per", "simple-pm-bus";
|
||||
power-domains = <&prm_l4per>;
|
||||
clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x48000000 0x800>,
|
||||
<0x48000800 0x800>,
|
||||
<0x48001000 0x400>,
|
||||
@ -1298,7 +1303,7 @@
|
||||
<0x00200000 0x48200000 0x200000>; /* segment 1 */
|
||||
|
||||
segment@0 { /* 0x48000000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -2437,7 +2442,7 @@
|
||||
};
|
||||
|
||||
segment@200000 { /* 0x48200000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
|
||||
|
||||
@ -22,6 +22,11 @@
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &mmc1;
|
||||
mmc1 = &mmc2;
|
||||
mmc2 = &mmc3;
|
||||
mmc3 = &mmc4;
|
||||
mmc4 = &mmc5;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
@ -54,14 +59,12 @@
|
||||
};
|
||||
|
||||
/*
|
||||
* Note that 4430 needs cross trigger interface (CTI) supported
|
||||
* before we can configure the interrupts. This means sampling
|
||||
* events are not supported for pmu. Note that 4460 does not use
|
||||
* CTI, see also 4460.dtsi.
|
||||
* Needed early by omap4_sram_init() for barrier, do not move to l3
|
||||
* interconnect as simple-pm-bus probes at module_init() time.
|
||||
*/
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
ti,hwmods = "debugss";
|
||||
ocmcram: sram@40304000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40304000 0xa000>; /* 40k */
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
@ -96,19 +99,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
sram = <&ocmcram>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
@ -117,16 +107,23 @@
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
power-domains = <&prm_l4per>;
|
||||
clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
|
||||
<&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
|
||||
<&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
reg = <0x44000000 0x1000>,
|
||||
<0x44800000 0x2000>,
|
||||
<0x45000000 0x1000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
l3-noc@44000000 {
|
||||
compatible = "ti,omap4-l3-noc";
|
||||
reg = <0x44000000 0x1000>,
|
||||
<0x44800000 0x2000>,
|
||||
<0x45000000 0x1000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
l4_wkup: interconnect@4a300000 {
|
||||
};
|
||||
@ -137,12 +134,22 @@
|
||||
l4_per: interconnect@48000000 {
|
||||
};
|
||||
|
||||
l4_abe: interconnect@40100000 {
|
||||
target-module@48210000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
power-domains = <&prm_mpu>;
|
||||
clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x48210000 0x1f0000>;
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
sram = <&ocmcram>;
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: sram@40304000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40304000 0xa000>; /* 40k */
|
||||
l4_abe: interconnect@40100000 {
|
||||
};
|
||||
|
||||
target-module@50000000 {
|
||||
@ -184,7 +191,6 @@
|
||||
|
||||
target-module@52000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
ti,hwmods = "iss";
|
||||
reg = <0x52000000 0x4>,
|
||||
<0x52000010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
@ -198,6 +204,7 @@
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-delay-us = <2>;
|
||||
power-domains = <&prm_cam>;
|
||||
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
@ -207,6 +214,26 @@
|
||||
/* No child device binding, driver in staging */
|
||||
};
|
||||
|
||||
/*
|
||||
* Note that 4430 needs cross trigger interface (CTI) supported
|
||||
* before we can configure the interrupts. This means sampling
|
||||
* events are not supported for pmu. Note that 4460 does not use
|
||||
* CTI, see also 4460.dtsi.
|
||||
*/
|
||||
target-module@54000000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
power-domains = <&prm_emu>;
|
||||
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x54000000 0x1000000>;
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@55082000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x55082000 0x4>,
|
||||
@ -256,35 +283,67 @@
|
||||
/* No child device binding or driver in mainline */
|
||||
};
|
||||
|
||||
dmm@4e000000 {
|
||||
compatible = "ti,omap4-dmm";
|
||||
reg = <0x4e000000 0x800>;
|
||||
interrupts = <0 113 0x4>;
|
||||
ti,hwmods = "dmm";
|
||||
target-module@4e000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x4e000000 0x4>,
|
||||
<0x4e000010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ranges = <0x0 0x4e000000 0x2000000>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
dmm@0 {
|
||||
compatible = "ti,omap4-dmm";
|
||||
reg = <0 0x800>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
emif1: emif@4c000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0x4c000000 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "emif1";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
target-module@4c000000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
reg = <0x4c000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
ti,no-idle;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4c000000 0x1000000>;
|
||||
|
||||
emif1: emif@0 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
};
|
||||
|
||||
emif2: emif@4d000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0x4d000000 0x100>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "emif2";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
target-module@4d000000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
reg = <0x4d000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
ti,no-idle;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4d000000 0x1000000>;
|
||||
|
||||
emif2: emif@0 {
|
||||
compatible = "ti,emif-4d";
|
||||
reg = <0 0x100>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-type = <1>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
};
|
||||
|
||||
dsp: dsp {
|
||||
@ -435,6 +494,7 @@
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
power-domains = <&prm_gfx>;
|
||||
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -26,13 +26,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "debugss";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
#include "omap4-cpu-thermal.dtsi"
|
||||
};
|
||||
@ -128,4 +121,10 @@
|
||||
<0x00030000 0x00030000 0x00010000>;
|
||||
};
|
||||
|
||||
&pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/include/ "omap446x-clocks.dtsi"
|
||||
|
||||
@ -770,14 +770,6 @@
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
sha2md5_fck: sha2md5_fck@15c8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l3_div_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x15c8>;
|
||||
};
|
||||
|
||||
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
|
||||
@ -1,5 +1,8 @@
|
||||
&l4_cfg { /* 0x4a000000 */
|
||||
compatible = "ti,omap5-l4-cfg", "simple-bus";
|
||||
compatible = "ti,omap5-l4-cfg", "simple-pm-bus";
|
||||
power-domains = <&prm_core>;
|
||||
clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x4a000000 0x800>,
|
||||
<0x4a000800 0x800>,
|
||||
<0x4a001000 0x1000>;
|
||||
@ -15,7 +18,7 @@
|
||||
<0x00300000 0x4a300000 0x080000>; /* segment 6 */
|
||||
|
||||
segment@0 { /* 0x4a000000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -391,7 +394,7 @@
|
||||
};
|
||||
|
||||
segment@80000 { /* 0x4a080000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
|
||||
@ -654,7 +657,7 @@
|
||||
};
|
||||
|
||||
segment@100000 { /* 0x4a100000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
|
||||
@ -691,22 +694,44 @@
|
||||
};
|
||||
|
||||
target-module@40000 { /* 0x4a140000, ap 101 16.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x400fc 4>,
|
||||
<0x41100 4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
power-domains = <&prm_l3init>;
|
||||
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges = <0x0 0x40000 0x10000>;
|
||||
|
||||
sata: sata@0 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0 0x1100>, <0x1100 0x8>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
segment@180000 { /* 0x4a180000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
segment@200000 { /* 0x4a200000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
|
||||
@ -912,20 +937,23 @@
|
||||
};
|
||||
|
||||
segment@280000 { /* 0x4a280000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
segment@300000 { /* 0x4a300000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&l4_per { /* 0x48000000 */
|
||||
compatible = "ti,omap5-l4-per", "simple-bus";
|
||||
compatible = "ti,omap5-l4-per", "simple-pm-bus";
|
||||
power-domains = <&prm_core>;
|
||||
clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x48000000 0x800>,
|
||||
<0x48000800 0x800>,
|
||||
<0x48001000 0x400>,
|
||||
@ -939,7 +967,7 @@
|
||||
<0x00200000 0x48200000 0x200000>; /* segment 1 */
|
||||
|
||||
segment@0 { /* 0x48000000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -2148,14 +2176,17 @@
|
||||
};
|
||||
|
||||
segment@200000 { /* 0x48200000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&l4_wkup { /* 0x4ae00000 */
|
||||
compatible = "ti,omap5-l4-wkup", "simple-bus";
|
||||
compatible = "ti,omap5-l4-wkup", "simple-pm-bus";
|
||||
power-domains = <&prm_wkupaon>;
|
||||
clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x4ae00000 0x800>,
|
||||
<0x4ae00800 0x800>,
|
||||
<0x4ae01000 0x1000>;
|
||||
@ -2167,7 +2198,7 @@
|
||||
<0x00020000 0x4ae20000 0x010000>; /* segment 2 */
|
||||
|
||||
segment@0 { /* 0x4ae00000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
||||
@ -2296,7 +2327,7 @@
|
||||
};
|
||||
|
||||
segment@10000 { /* 0x4ae10000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
|
||||
@ -2423,7 +2454,7 @@
|
||||
};
|
||||
|
||||
segment@20000 { /* 0x4ae20000 */
|
||||
compatible = "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
|
||||
|
||||
@ -25,6 +25,11 @@
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
i2c4 = &i2c5;
|
||||
mmc0 = &mmc1;
|
||||
mmc1 = &mmc2;
|
||||
mmc2 = &mmc3;
|
||||
mmc3 = &mmc4;
|
||||
mmc4 = &mmc5;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
@ -101,6 +106,15 @@
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Needed early by omap4_sram_init() for barrier, do not move to l3
|
||||
* interconnect as simple-pm-bus probes at module_init() time.
|
||||
*/
|
||||
ocmcram: sram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0x40300000 0 0x20000>; /* 128k */
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48211000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
@ -120,19 +134,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
sram = <&ocmcram>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
@ -141,17 +142,24 @@
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap5-l3-noc", "simple-bus";
|
||||
compatible = "simple-pm-bus";
|
||||
power-domains = <&prm_core>;
|
||||
clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
|
||||
<&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
|
||||
<&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xc0000000>;
|
||||
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
reg = <0 0x44000000 0 0x2000>,
|
||||
<0 0x44800000 0 0x3000>,
|
||||
<0 0x45000000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
l3-noc@44000000 {
|
||||
compatible = "ti,omap5-l3-noc";
|
||||
reg = <0x44000000 0x2000>,
|
||||
<0x44800000 0x3000>,
|
||||
<0x45000000 0x4000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
l4_wkup: interconnect@4ae00000 {
|
||||
};
|
||||
@ -162,31 +170,58 @@
|
||||
l4_per: interconnect@48000000 {
|
||||
};
|
||||
|
||||
target-module@48210000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
power-domains = <&prm_mpu>;
|
||||
clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x48210000 0x1f0000>;
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
sram = <&ocmcram>;
|
||||
};
|
||||
};
|
||||
|
||||
l4_abe: interconnect@40100000 {
|
||||
};
|
||||
|
||||
ocmcram: sram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x20000>; /* 128k */
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,omap4430-gpmc";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 4>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
ti,hwmods = "gpmc";
|
||||
clocks = <&l3_iclk_div>;
|
||||
target-module@50000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x50000000 4>,
|
||||
<0x50000010 4>,
|
||||
<0x50000014 4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
ti,no-idle-on-init;
|
||||
clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
|
||||
<0x00000000 0x00000000 0x40000000>; /* data */
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,omap4430-gpmc";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 4>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
clock-names = "fck";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@55082000 {
|
||||
@ -241,35 +276,67 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmm@4e000000 {
|
||||
compatible = "ti,omap5-dmm";
|
||||
reg = <0x4e000000 0x800>;
|
||||
interrupts = <0 113 0x4>;
|
||||
ti,hwmods = "dmm";
|
||||
target-module@4e000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x4e000000 0x4>,
|
||||
<0x4e000010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ranges = <0x0 0x4e000000 0x2000000>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
dmm@0 {
|
||||
compatible = "ti,omap5-dmm";
|
||||
reg = <0 0x800>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
emif1: emif@4c000000 {
|
||||
compatible = "ti,emif-4d5";
|
||||
ti,hwmods = "emif1";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
reg = <0x4c000000 0x400>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
target-module@4c000000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
reg = <0x4c000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
ti,no-idle;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4c000000 0x1000000>;
|
||||
|
||||
emif1: emif@0 {
|
||||
compatible = "ti,emif-4d5";
|
||||
reg = <0 0x400>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
};
|
||||
|
||||
emif2: emif@4d000000 {
|
||||
compatible = "ti,emif-4d5";
|
||||
ti,hwmods = "emif2";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
reg = <0x4d000000 0x400>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
target-module@4d000000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
reg = <0x4d000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
ti,no-idle;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x4d000000 0x1000000>;
|
||||
|
||||
emif2: emif@0 {
|
||||
compatible = "ti,emif-4d5";
|
||||
reg = <0 0x400>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
};
|
||||
|
||||
aes1_target: target-module@4b501000 {
|
||||
@ -369,18 +436,6 @@
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
/* OCP2SCP3 */
|
||||
sata: sata@4a141100 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
|
||||
ti,hwmods = "sata";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
|
||||
@ -34,7 +34,6 @@ config ARCH_OMAP4
|
||||
select ARM_GIC
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
@ -54,7 +53,6 @@ config SOC_OMAP5
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PM_OPP
|
||||
@ -90,7 +88,6 @@ config SOC_DRA7XX
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select IRQ_CROSSBAR
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PM_OPP
|
||||
|
||||
@ -20,14 +20,14 @@ secure-common = omap-smc.o omap-secure.o
|
||||
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(secure-common)
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(secure-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(secure-common)
|
||||
|
||||
ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),)
|
||||
obj-y += mcbsp.o
|
||||
obj-$(CONFIG_OMAP_HWMOD) += mcbsp.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
|
||||
@ -207,9 +207,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
|
||||
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
|
||||
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
|
||||
obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
|
||||
|
||||
# OMAP2420 MSDI controller integration support ("MMC")
|
||||
obj-$(CONFIG_SOC_OMAP2420) += msdi.o
|
||||
|
||||
@ -343,15 +343,6 @@ static inline void omap5_secondary_hyp_startup(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_DRA7XX
|
||||
extern int dra7xx_pciess_reset(struct omap_hwmod *oh);
|
||||
#else
|
||||
static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct omap_system_dma_plat_info;
|
||||
|
||||
void pdata_quirks_init(const struct of_device_id *);
|
||||
|
||||
@ -402,6 +402,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
|
||||
return v;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
|
||||
{
|
||||
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
|
||||
@ -414,6 +415,11 @@ static void __init __maybe_unused omap_hwmod_init_postsetup(void)
|
||||
/* Set the default postsetup state for all hwmods */
|
||||
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
|
||||
}
|
||||
#else
|
||||
static inline void omap_hwmod_init_postsetup(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
void __init omap2420_init_early(void)
|
||||
@ -615,8 +621,6 @@ void __init omap4430_init_early(void)
|
||||
omap44xx_voltagedomains_init();
|
||||
omap44xx_powerdomains_init();
|
||||
omap44xx_clockdomains_init();
|
||||
omap44xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_l2_cache_init();
|
||||
omap_clk_soc_init = omap4xxx_dt_clk_init;
|
||||
omap_secure_init();
|
||||
@ -643,8 +647,6 @@ void __init omap5_init_early(void)
|
||||
omap54xx_voltagedomains_init();
|
||||
omap54xx_powerdomains_init();
|
||||
omap54xx_clockdomains_init();
|
||||
omap54xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = omap5xxx_dt_clk_init;
|
||||
omap_secure_init();
|
||||
}
|
||||
@ -667,8 +669,6 @@ void __init dra7xx_init_early(void)
|
||||
dra7xxx_check_revision();
|
||||
dra7xx_powerdomains_init();
|
||||
dra7xx_clockdomains_init();
|
||||
dra7xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = dra7xx_dt_clk_init;
|
||||
omap_secure_init();
|
||||
}
|
||||
|
||||
@ -3495,10 +3495,6 @@ static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
|
||||
{ .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
|
||||
};
|
||||
|
||||
static const struct omap_hwmod_reset dra7_reset_quirks[] = {
|
||||
{ .match = "pcie", .len = 4, .reset = dra7xx_pciess_reset, },
|
||||
};
|
||||
|
||||
static const struct omap_hwmod_reset omap_reset_quirks[] = {
|
||||
{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
|
||||
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
|
||||
@ -3534,10 +3530,6 @@ omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
|
||||
omap24xx_reset_quirks,
|
||||
ARRAY_SIZE(omap24xx_reset_quirks));
|
||||
|
||||
if (soc_is_dra7xx())
|
||||
omap_hwmod_init_reset_quirk(dev, oh, data, dra7_reset_quirks,
|
||||
ARRAY_SIZE(dra7_reset_quirks));
|
||||
|
||||
omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
|
||||
ARRAY_SIZE(omap_reset_quirks));
|
||||
}
|
||||
|
||||
@ -607,6 +607,8 @@ struct omap_hwmod {
|
||||
struct omap_hwmod *parent_hwmod;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
|
||||
struct device_node;
|
||||
|
||||
struct omap_hwmod *omap_hwmod_lookup(const char *name);
|
||||
@ -656,6 +658,17 @@ extern void __init omap_hwmod_init(void);
|
||||
|
||||
const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
|
||||
|
||||
#else /* CONFIG_OMAP_HWMOD */
|
||||
|
||||
static inline int
|
||||
omap_hwmod_for_each_by_class(const char *classname,
|
||||
int (*fn)(struct omap_hwmod *oh, void *user),
|
||||
void *user)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OMAP_HWMOD */
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
@ -671,7 +684,6 @@ extern int omap2420_hwmod_init(void);
|
||||
extern int omap2430_hwmod_init(void);
|
||||
extern int omap3xxx_hwmod_init(void);
|
||||
extern int omap44xx_hwmod_init(void);
|
||||
extern int omap54xx_hwmod_init(void);
|
||||
extern int am33xx_hwmod_init(void);
|
||||
extern int dm814x_hwmod_init(void);
|
||||
extern int dm816x_hwmod_init(void);
|
||||
|
||||
@ -1,877 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Hardware modules present on the OMAP44xx chips
|
||||
*
|
||||
* Copyright (C) 2009-2012 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley
|
||||
* Benoit Cousson
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
* Note that this file is currently not in sync with autogeneration scripts.
|
||||
* The above note to be removed, once it is synced up.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "omap_hwmod.h"
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "cm1_44xx.h"
|
||||
#include "cm2_44xx.h"
|
||||
#include "prm44xx.h"
|
||||
#include "prm-regbits-44xx.h"
|
||||
|
||||
/* Base offset for all OMAP4 interrupts external to MPUSS */
|
||||
#define OMAP44XX_IRQ_GIC_START 32
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'dmm' class
|
||||
* instance(s): dmm
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
|
||||
.name = "dmm",
|
||||
};
|
||||
|
||||
/* dmm */
|
||||
static struct omap_hwmod omap44xx_dmm_hwmod = {
|
||||
.name = "dmm",
|
||||
.class = &omap44xx_dmm_hwmod_class,
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l3' class
|
||||
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
|
||||
.name = "l3",
|
||||
};
|
||||
|
||||
/* l3_instr */
|
||||
static struct omap_hwmod omap44xx_l3_instr_hwmod = {
|
||||
.name = "l3_instr",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_1 */
|
||||
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
|
||||
.name = "l3_main_1",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_2 */
|
||||
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
|
||||
.name = "l3_main_2",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_3 */
|
||||
static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
|
||||
.name = "l3_main_3",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l4' class
|
||||
* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
|
||||
.name = "l4",
|
||||
};
|
||||
|
||||
/* l4_cfg */
|
||||
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
|
||||
.name = "l4_cfg",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_per */
|
||||
static struct omap_hwmod omap44xx_l4_per_hwmod = {
|
||||
.name = "l4_per",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_wkup */
|
||||
static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu_bus' class
|
||||
* instance(s): mpu_private
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
|
||||
.name = "mpu_bus",
|
||||
};
|
||||
|
||||
/* mpu_private */
|
||||
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
|
||||
.name = "mpu_private",
|
||||
.class = &omap44xx_mpu_bus_hwmod_class,
|
||||
.clkdm_name = "mpuss_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'ocp_wp_noc' class
|
||||
* instance(s): ocp_wp_noc
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
|
||||
.name = "ocp_wp_noc",
|
||||
};
|
||||
|
||||
/* ocp_wp_noc */
|
||||
static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
|
||||
.name = "ocp_wp_noc",
|
||||
.class = &omap44xx_ocp_wp_noc_hwmod_class,
|
||||
.clkdm_name = "l3_instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Modules omap_hwmod structures
|
||||
*
|
||||
* The following IPs are excluded for the moment because:
|
||||
* - They do not need an explicit SW control using omap_hwmod API.
|
||||
* - They still need to be validated with the driver
|
||||
* properly adapted to omap_hwmod / omap_device
|
||||
*
|
||||
* usim
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'ctrl_module' class
|
||||
* attila core control module + core pad control module + wkup pad control
|
||||
* module + attila wkup control module
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
|
||||
.name = "ctrl_module",
|
||||
.sysc = &omap44xx_ctrl_module_sysc,
|
||||
};
|
||||
|
||||
/* ctrl_module_core */
|
||||
static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
|
||||
.name = "ctrl_module_core",
|
||||
.class = &omap44xx_ctrl_module_hwmod_class,
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* ctrl_module_pad_core */
|
||||
static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
|
||||
.name = "ctrl_module_pad_core",
|
||||
.class = &omap44xx_ctrl_module_hwmod_class,
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* ctrl_module_wkup */
|
||||
static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
|
||||
.name = "ctrl_module_wkup",
|
||||
.class = &omap44xx_ctrl_module_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* ctrl_module_pad_wkup */
|
||||
static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
|
||||
.name = "ctrl_module_pad_wkup",
|
||||
.class = &omap44xx_ctrl_module_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'debugss' class
|
||||
* debug and emulation sub system
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
|
||||
.name = "debugss",
|
||||
};
|
||||
|
||||
/* debugss */
|
||||
static struct omap_hwmod omap44xx_debugss_hwmod = {
|
||||
.name = "debugss",
|
||||
.class = &omap44xx_debugss_hwmod_class,
|
||||
.clkdm_name = "emu_sys_clkdm",
|
||||
.main_clk = "trace_clk_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'emif' class
|
||||
* external memory interface no1
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
|
||||
.name = "emif",
|
||||
.sysc = &omap44xx_emif_sysc,
|
||||
};
|
||||
|
||||
/* emif1 */
|
||||
static struct omap_hwmod omap44xx_emif1_hwmod = {
|
||||
.name = "emif1",
|
||||
.class = &omap44xx_emif_hwmod_class,
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "ddrphy_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* emif2 */
|
||||
static struct omap_hwmod omap44xx_emif2_hwmod = {
|
||||
.name = "emif2",
|
||||
.class = &omap44xx_emif_hwmod_class,
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "ddrphy_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'iss' class
|
||||
* external images sensor pixel data processor
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
/*
|
||||
* ISS needs 100 OCP clk cycles delay after a softreset before
|
||||
* accessing sysconfig again.
|
||||
* The lowest frequency at the moment for L3 bus is 100 MHz, so
|
||||
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
|
||||
*
|
||||
* TODO: Indicate errata when available.
|
||||
*/
|
||||
.srst_udelay = 2,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
|
||||
.name = "iss",
|
||||
.sysc = &omap44xx_iss_sysc,
|
||||
};
|
||||
|
||||
/* iss */
|
||||
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
|
||||
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_iss_hwmod = {
|
||||
.name = "iss",
|
||||
.class = &omap44xx_iss_hwmod_class,
|
||||
.clkdm_name = "iss_clkdm",
|
||||
.main_clk = "ducati_clk_mux_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.opt_clks = iss_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
* mpu sub-system
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
|
||||
.name = "mpu",
|
||||
};
|
||||
|
||||
/* mpu */
|
||||
static struct omap_hwmod omap44xx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &omap44xx_mpu_hwmod_class,
|
||||
.clkdm_name = "mpuss_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_mpu_m2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'ocmc_ram' class
|
||||
* top-level core on-chip ram
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
|
||||
.name = "ocmc_ram",
|
||||
};
|
||||
|
||||
/* ocmc_ram */
|
||||
static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
|
||||
.name = "ocmc_ram",
|
||||
.class = &omap44xx_ocmc_ram_hwmod_class,
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 'prcm' class
|
||||
* power and reset manager (part of the prcm infrastructure) + clock manager 2
|
||||
* + clock manager 1 (in always on power domain) + local prm in mpu
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
|
||||
.name = "prcm",
|
||||
};
|
||||
|
||||
/* prcm_mpu */
|
||||
static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
|
||||
.name = "prcm_mpu",
|
||||
.class = &omap44xx_prcm_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* cm_core_aon */
|
||||
static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
|
||||
.name = "cm_core_aon",
|
||||
.class = &omap44xx_prcm_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* cm_core */
|
||||
static struct omap_hwmod omap44xx_cm_core_hwmod = {
|
||||
.name = "cm_core",
|
||||
.class = &omap44xx_prcm_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* prm */
|
||||
static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
|
||||
{ .name = "rst_global_warm_sw", .rst_shift = 0 },
|
||||
{ .name = "rst_global_cold_sw", .rst_shift = 1 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_prm_hwmod = {
|
||||
.name = "prm",
|
||||
.class = &omap44xx_prcm_hwmod_class,
|
||||
.rst_lines = omap44xx_prm_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'scrm' class
|
||||
* system clock and reset manager
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
|
||||
.name = "scrm",
|
||||
};
|
||||
|
||||
/* scrm */
|
||||
static struct omap_hwmod omap44xx_scrm_hwmod = {
|
||||
.name = "scrm",
|
||||
.class = &omap44xx_scrm_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'sl2if' class
|
||||
* shared level 2 memory interface
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
|
||||
.name = "sl2if",
|
||||
};
|
||||
|
||||
/* sl2if */
|
||||
static struct omap_hwmod omap44xx_sl2if_hwmod = {
|
||||
.name = "sl2if",
|
||||
.class = &omap44xx_sl2if_hwmod_class,
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* interfaces
|
||||
*/
|
||||
|
||||
/* l3_main_1 -> dmm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_dmm_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> dmm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_dmm_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_3 -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
|
||||
.master = &omap44xx_l3_main_3_hwmod,
|
||||
.slave = &omap44xx_l3_instr_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* ocp_wp_noc -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
|
||||
.master = &omap44xx_ocp_wp_noc_hwmod,
|
||||
.slave = &omap44xx_l3_instr_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* debugss -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
|
||||
.master = &omap44xx_debugss_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "dbgclk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* iss -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
|
||||
.master = &omap44xx_iss_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_cfg */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l4_cfg_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l4_per */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l4_per_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l4_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l4_wkup_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> mpu_private */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_mpu_private_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> ocp_wp_noc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_ocp_wp_noc_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> ctrl_module_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> ctrl_module_pad_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_pad_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> ctrl_module_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_wkup_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> ctrl_module_pad_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_instr -> debugss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
|
||||
.master = &omap44xx_l3_instr_hwmod,
|
||||
.slave = &omap44xx_debugss_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> iss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_iss_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> ocmc_ram */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_ocmc_ram_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu_private -> prcm_mpu */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
|
||||
.master = &omap44xx_mpu_private_hwmod,
|
||||
.slave = &omap44xx_prcm_mpu_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> cm_core_aon */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_cm_core_aon_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> cm_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_cm_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> prm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_prm_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> scrm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_scrm_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> sl2if */
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_sl2if_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> emif1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_emif1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> emif2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_emif2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l3_main_1__dmm,
|
||||
&omap44xx_mpu__dmm,
|
||||
&omap44xx_l3_main_3__l3_instr,
|
||||
&omap44xx_ocp_wp_noc__l3_instr,
|
||||
&omap44xx_l3_main_2__l3_main_1,
|
||||
&omap44xx_l4_cfg__l3_main_1,
|
||||
&omap44xx_mpu__l3_main_1,
|
||||
&omap44xx_debugss__l3_main_2,
|
||||
&omap44xx_iss__l3_main_2,
|
||||
&omap44xx_l3_main_1__l3_main_2,
|
||||
&omap44xx_l4_cfg__l3_main_2,
|
||||
&omap44xx_l3_main_1__l3_main_3,
|
||||
&omap44xx_l3_main_2__l3_main_3,
|
||||
&omap44xx_l4_cfg__l3_main_3,
|
||||
&omap44xx_l3_main_1__l4_cfg,
|
||||
&omap44xx_l3_main_2__l4_per,
|
||||
&omap44xx_l4_cfg__l4_wkup,
|
||||
&omap44xx_mpu__mpu_private,
|
||||
&omap44xx_l4_cfg__ocp_wp_noc,
|
||||
&omap44xx_l4_cfg__ctrl_module_core,
|
||||
&omap44xx_l4_cfg__ctrl_module_pad_core,
|
||||
&omap44xx_l4_wkup__ctrl_module_wkup,
|
||||
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
|
||||
&omap44xx_l3_instr__debugss,
|
||||
&omap44xx_l3_main_2__iss,
|
||||
&omap44xx_l3_main_2__ocmc_ram,
|
||||
&omap44xx_mpu_private__prcm_mpu,
|
||||
&omap44xx_l4_wkup__cm_core_aon,
|
||||
&omap44xx_l4_cfg__cm_core,
|
||||
&omap44xx_l4_wkup__prm,
|
||||
&omap44xx_l4_wkup__scrm,
|
||||
/* &omap44xx_l3_main_2__sl2if, */
|
||||
&omap44xx_mpu__emif1,
|
||||
&omap44xx_mpu__emif2,
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init omap44xx_hwmod_init(void)
|
||||
{
|
||||
omap_hwmod_init();
|
||||
return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
|
||||
}
|
||||
|
||||
@ -1,467 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Hardware modules present on the OMAP54xx chips
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
|
||||
*
|
||||
* Paul Walmsley
|
||||
* Benoit Cousson
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/power/smartreflex.h>
|
||||
|
||||
#include "omap_hwmod.h"
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "cm1_54xx.h"
|
||||
#include "cm2_54xx.h"
|
||||
#include "prm54xx.h"
|
||||
|
||||
/* Base offset for all OMAP5 interrupts external to MPUSS */
|
||||
#define OMAP54XX_IRQ_GIC_START 32
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'dmm' class
|
||||
* instance(s): dmm
|
||||
*/
|
||||
static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
|
||||
.name = "dmm",
|
||||
};
|
||||
|
||||
/* dmm */
|
||||
static struct omap_hwmod omap54xx_dmm_hwmod = {
|
||||
.name = "dmm",
|
||||
.class = &omap54xx_dmm_hwmod_class,
|
||||
.clkdm_name = "emif_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l3' class
|
||||
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
|
||||
*/
|
||||
static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
|
||||
.name = "l3",
|
||||
};
|
||||
|
||||
/* l3_instr */
|
||||
static struct omap_hwmod omap54xx_l3_instr_hwmod = {
|
||||
.name = "l3_instr",
|
||||
.class = &omap54xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_1 */
|
||||
static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
|
||||
.name = "l3_main_1",
|
||||
.class = &omap54xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3main1_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_2 */
|
||||
static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
|
||||
.name = "l3_main_2",
|
||||
.class = &omap54xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3main2_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_3 */
|
||||
static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
|
||||
.name = "l3_main_3",
|
||||
.class = &omap54xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l4' class
|
||||
* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
|
||||
*/
|
||||
static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
|
||||
.name = "l4",
|
||||
};
|
||||
|
||||
/* l4_cfg */
|
||||
static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
|
||||
.name = "l4_cfg",
|
||||
.class = &omap54xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4cfg_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_per */
|
||||
static struct omap_hwmod omap54xx_l4_per_hwmod = {
|
||||
.name = "l4_per",
|
||||
.class = &omap54xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_wkup */
|
||||
static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &omap54xx_l4_hwmod_class,
|
||||
.clkdm_name = "wkupaon_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu_bus' class
|
||||
* instance(s): mpu_private
|
||||
*/
|
||||
static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
|
||||
.name = "mpu_bus",
|
||||
};
|
||||
|
||||
/* mpu_private */
|
||||
static struct omap_hwmod omap54xx_mpu_private_hwmod = {
|
||||
.name = "mpu_private",
|
||||
.class = &omap54xx_mpu_bus_hwmod_class,
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'emif' class
|
||||
* external memory interface no1 (wrapper)
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
|
||||
.name = "emif",
|
||||
.sysc = &omap54xx_emif_sysc,
|
||||
};
|
||||
|
||||
/* emif1 */
|
||||
static struct omap_hwmod omap54xx_emif1_hwmod = {
|
||||
.name = "emif1",
|
||||
.class = &omap54xx_emif_hwmod_class,
|
||||
.clkdm_name = "emif_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_core_h11x2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* emif2 */
|
||||
static struct omap_hwmod omap54xx_emif2_hwmod = {
|
||||
.name = "emif2",
|
||||
.class = &omap54xx_emif_hwmod_class,
|
||||
.clkdm_name = "emif_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_core_h11x2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
* mpu sub-system
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
|
||||
.name = "mpu",
|
||||
};
|
||||
|
||||
/* mpu */
|
||||
static struct omap_hwmod omap54xx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &omap54xx_mpu_hwmod_class,
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_mpu_m2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'sata' class
|
||||
* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
|
||||
.rev_offs = 0x00fc,
|
||||
.sysc_offs = 0x0000,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
|
||||
.name = "sata",
|
||||
.sysc = &omap54xx_sata_sysc,
|
||||
};
|
||||
|
||||
/* sata */
|
||||
static struct omap_hwmod omap54xx_sata_hwmod = {
|
||||
.name = "sata",
|
||||
.class = &omap54xx_sata_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.mpu_rt_idx = 1,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_cfg -> sata */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_sata_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interfaces
|
||||
*/
|
||||
|
||||
/* l3_main_1 -> dmm */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
|
||||
.master = &omap54xx_l3_main_1_hwmod,
|
||||
.slave = &omap54xx_dmm_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_3 -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
|
||||
.master = &omap54xx_l3_main_3_hwmod,
|
||||
.slave = &omap54xx_l3_instr_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
|
||||
.master = &omap54xx_l3_main_2_hwmod,
|
||||
.slave = &omap54xx_l3_main_1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_l3_main_1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
|
||||
.master = &omap54xx_mpu_hwmod,
|
||||
.slave = &omap54xx_l3_main_1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
|
||||
.master = &omap54xx_l3_main_1_hwmod,
|
||||
.slave = &omap54xx_l3_main_2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_l3_main_2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
|
||||
.master = &omap54xx_l3_main_1_hwmod,
|
||||
.slave = &omap54xx_l3_main_3_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
|
||||
.master = &omap54xx_l3_main_2_hwmod,
|
||||
.slave = &omap54xx_l3_main_3_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_l3_main_3_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_cfg */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
|
||||
.master = &omap54xx_l3_main_1_hwmod,
|
||||
.slave = &omap54xx_l4_cfg_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l4_per */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
|
||||
.master = &omap54xx_l3_main_2_hwmod,
|
||||
.slave = &omap54xx_l4_per_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_wkup */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
|
||||
.master = &omap54xx_l3_main_1_hwmod,
|
||||
.slave = &omap54xx_l4_wkup_hwmod,
|
||||
.clk = "wkupaon_iclk_mux",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> mpu_private */
|
||||
static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
|
||||
.master = &omap54xx_mpu_hwmod,
|
||||
.slave = &omap54xx_mpu_private_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> emif1 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
|
||||
.master = &omap54xx_mpu_hwmod,
|
||||
.slave = &omap54xx_emif1_hwmod,
|
||||
.clk = "dpll_core_h11x2_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> emif2 */
|
||||
static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
|
||||
.master = &omap54xx_mpu_hwmod,
|
||||
.slave = &omap54xx_emif2_hwmod,
|
||||
.clk = "dpll_core_h11x2_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> mpu */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_mpu_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap54xx_l3_main_1__dmm,
|
||||
&omap54xx_l3_main_3__l3_instr,
|
||||
&omap54xx_l3_main_2__l3_main_1,
|
||||
&omap54xx_l4_cfg__l3_main_1,
|
||||
&omap54xx_mpu__l3_main_1,
|
||||
&omap54xx_l3_main_1__l3_main_2,
|
||||
&omap54xx_l4_cfg__l3_main_2,
|
||||
&omap54xx_l3_main_1__l3_main_3,
|
||||
&omap54xx_l3_main_2__l3_main_3,
|
||||
&omap54xx_l4_cfg__l3_main_3,
|
||||
&omap54xx_l3_main_1__l4_cfg,
|
||||
&omap54xx_l3_main_2__l4_per,
|
||||
&omap54xx_l3_main_1__l4_wkup,
|
||||
&omap54xx_mpu__mpu_private,
|
||||
&omap54xx_mpu__emif1,
|
||||
&omap54xx_mpu__emif2,
|
||||
&omap54xx_l4_cfg__mpu,
|
||||
&omap54xx_l4_cfg__sata,
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init omap54xx_hwmod_init(void)
|
||||
{
|
||||
omap_hwmod_init();
|
||||
return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
|
||||
}
|
||||
@ -1,719 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Hardware modules present on the DRA7xx chips
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
|
||||
*
|
||||
* Paul Walmsley
|
||||
* Benoit Cousson
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "omap_hwmod.h"
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "cm1_7xx.h"
|
||||
#include "cm2_7xx.h"
|
||||
#include "prm7xx.h"
|
||||
#include "soc.h"
|
||||
|
||||
/* Base offset for all DRA7XX interrupts external to MPUSS */
|
||||
#define DRA7XX_IRQ_GIC_START 32
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'dmm' class
|
||||
* instance(s): dmm
|
||||
*/
|
||||
static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
|
||||
.name = "dmm",
|
||||
};
|
||||
|
||||
/* dmm */
|
||||
static struct omap_hwmod dra7xx_dmm_hwmod = {
|
||||
.name = "dmm",
|
||||
.class = &dra7xx_dmm_hwmod_class,
|
||||
.clkdm_name = "emif_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l3' class
|
||||
* instance(s): l3_instr, l3_main_1, l3_main_2
|
||||
*/
|
||||
static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
|
||||
.name = "l3",
|
||||
};
|
||||
|
||||
/* l3_instr */
|
||||
static struct omap_hwmod dra7xx_l3_instr_hwmod = {
|
||||
.name = "l3_instr",
|
||||
.class = &dra7xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_1 */
|
||||
static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
|
||||
.name = "l3_main_1",
|
||||
.class = &dra7xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3main1_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l3_main_2 */
|
||||
static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
|
||||
.name = "l3_main_2",
|
||||
.class = &dra7xx_l3_hwmod_class,
|
||||
.clkdm_name = "l3instr_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l4' class
|
||||
* instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
|
||||
*/
|
||||
static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
|
||||
.name = "l4",
|
||||
};
|
||||
|
||||
/* l4_cfg */
|
||||
static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
|
||||
.name = "l4_cfg",
|
||||
.class = &dra7xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4cfg_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_per1 */
|
||||
static struct omap_hwmod dra7xx_l4_per1_hwmod = {
|
||||
.name = "l4_per1",
|
||||
.class = &dra7xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_per2 */
|
||||
static struct omap_hwmod dra7xx_l4_per2_hwmod = {
|
||||
.name = "l4_per2",
|
||||
.class = &dra7xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4per2_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_per3 */
|
||||
static struct omap_hwmod dra7xx_l4_per3_hwmod = {
|
||||
.name = "l4_per3",
|
||||
.class = &dra7xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4per3_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_wkup */
|
||||
static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &dra7xx_l4_hwmod_class,
|
||||
.clkdm_name = "wkupaon_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'atl' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
|
||||
.name = "atl",
|
||||
};
|
||||
|
||||
/* atl */
|
||||
static struct omap_hwmod dra7xx_atl_hwmod = {
|
||||
.name = "atl",
|
||||
.class = &dra7xx_atl_hwmod_class,
|
||||
.clkdm_name = "atl_clkdm",
|
||||
.main_clk = "atl_gfclk_mux",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'bb2d' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
|
||||
.name = "bb2d",
|
||||
};
|
||||
|
||||
/* bb2d */
|
||||
static struct omap_hwmod dra7xx_bb2d_hwmod = {
|
||||
.name = "bb2d",
|
||||
.class = &dra7xx_bb2d_hwmod_class,
|
||||
.clkdm_name = "dss_clkdm",
|
||||
.main_clk = "dpll_core_h24x2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'ctrl_module' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
|
||||
.name = "ctrl_module",
|
||||
};
|
||||
|
||||
/* ctrl_module_wkup */
|
||||
static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
|
||||
.name = "ctrl_module_wkup",
|
||||
.class = &dra7xx_ctrl_module_hwmod_class,
|
||||
.clkdm_name = "wkupaon_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
|
||||
.name = "mpu",
|
||||
};
|
||||
|
||||
/* mpu */
|
||||
static struct omap_hwmod dra7xx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &dra7xx_mpu_hwmod_class,
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
||||
.main_clk = "dpll_mpu_m2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 'PCIE' class
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* As noted in documentation for _reset() in omap_hwmod.c, the stock reset
|
||||
* functionality of OMAP HWMOD layer does not deassert the hardreset lines
|
||||
* associated with an IP automatically leaving the driver to handle that
|
||||
* by itself. This does not work for PCIeSS which needs the reset lines
|
||||
* deasserted for the driver to start accessing registers.
|
||||
*
|
||||
* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
|
||||
* lines after asserting them.
|
||||
*/
|
||||
int dra7xx_pciess_reset(struct omap_hwmod *oh)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < oh->rst_lines_cnt; i++) {
|
||||
omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
|
||||
omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
|
||||
.name = "pcie",
|
||||
.reset = dra7xx_pciess_reset,
|
||||
};
|
||||
|
||||
/* pcie1 */
|
||||
static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
|
||||
{ .name = "pcie", .rst_shift = 0 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod dra7xx_pciess1_hwmod = {
|
||||
.name = "pcie1",
|
||||
.class = &dra7xx_pciess_hwmod_class,
|
||||
.clkdm_name = "pcie_clkdm",
|
||||
.rst_lines = dra7xx_pciess1_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
|
||||
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* pcie2 */
|
||||
static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
|
||||
{ .name = "pcie", .rst_shift = 1 },
|
||||
};
|
||||
|
||||
/* pcie2 */
|
||||
static struct omap_hwmod dra7xx_pciess2_hwmod = {
|
||||
.name = "pcie2",
|
||||
.class = &dra7xx_pciess_hwmod_class,
|
||||
.clkdm_name = "pcie_clkdm",
|
||||
.rst_lines = dra7xx_pciess2_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
|
||||
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'qspi' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
|
||||
.rev_offs = 0,
|
||||
.sysc_offs = 0x0010,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
|
||||
.name = "qspi",
|
||||
.sysc = &dra7xx_qspi_sysc,
|
||||
};
|
||||
|
||||
/* qspi */
|
||||
static struct omap_hwmod dra7xx_qspi_hwmod = {
|
||||
.name = "qspi",
|
||||
.class = &dra7xx_qspi_hwmod_class,
|
||||
.clkdm_name = "l4per2_clkdm",
|
||||
.main_clk = "qspi_gfclk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'sata' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
|
||||
.rev_offs = 0x00fc,
|
||||
.sysc_offs = 0x0000,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
|
||||
.name = "sata",
|
||||
.sysc = &dra7xx_sata_sysc,
|
||||
};
|
||||
|
||||
/* sata */
|
||||
|
||||
static struct omap_hwmod dra7xx_sata_hwmod = {
|
||||
.name = "sata",
|
||||
.class = &dra7xx_sata_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.main_clk = "func_48m_fclk",
|
||||
.mpu_rt_idx = 1,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'vcp' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
|
||||
.name = "vcp",
|
||||
};
|
||||
|
||||
/* vcp1 */
|
||||
static struct omap_hwmod dra7xx_vcp1_hwmod = {
|
||||
.name = "vcp1",
|
||||
.class = &dra7xx_vcp_hwmod_class,
|
||||
.clkdm_name = "l3main1_clkdm",
|
||||
.main_clk = "l3_iclk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* vcp2 */
|
||||
static struct omap_hwmod dra7xx_vcp2_hwmod = {
|
||||
.name = "vcp2",
|
||||
.class = &dra7xx_vcp_hwmod_class,
|
||||
.clkdm_name = "l3main1_clkdm",
|
||||
.main_clk = "l3_iclk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Interfaces
|
||||
*/
|
||||
|
||||
/* l3_main_1 -> dmm */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_dmm_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
|
||||
.master = &dra7xx_l3_main_2_hwmod,
|
||||
.slave = &dra7xx_l3_instr_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_l3_main_1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
|
||||
.master = &dra7xx_mpu_hwmod,
|
||||
.slave = &dra7xx_l3_main_1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l3_main_2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_l3_main_2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_cfg */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l4_cfg_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_per1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l4_per1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_per2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l4_per2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_per3 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l4_per3_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l4_wkup */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_l4_wkup_hwmod,
|
||||
.clk = "wkupaon_iclk_mux",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_per2 -> atl */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
|
||||
.master = &dra7xx_l4_per2_hwmod,
|
||||
.slave = &dra7xx_atl_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> bb2d */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_bb2d_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> ctrl_module_wkup */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
|
||||
.master = &dra7xx_l4_wkup_hwmod,
|
||||
.slave = &dra7xx_ctrl_module_wkup_hwmod,
|
||||
.clk = "wkupaon_iclk_mux",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> mpu */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_mpu_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> pciess1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_pciess1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pciess1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pciess1_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> pciess2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_pciess2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> pciess2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_pciess2_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> qspi */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_qspi_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> sata */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_sata_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> vcp1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_vcp1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_per2 -> vcp1 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
|
||||
.master = &dra7xx_l4_per2_hwmod,
|
||||
.slave = &dra7xx_vcp1_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> vcp2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_vcp2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_per2 -> vcp2 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
|
||||
.master = &dra7xx_l4_per2_hwmod,
|
||||
.slave = &dra7xx_vcp2_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l3_main_1__dmm,
|
||||
&dra7xx_l3_main_2__l3_instr,
|
||||
&dra7xx_l4_cfg__l3_main_1,
|
||||
&dra7xx_mpu__l3_main_1,
|
||||
&dra7xx_l3_main_1__l3_main_2,
|
||||
&dra7xx_l4_cfg__l3_main_2,
|
||||
&dra7xx_l3_main_1__l4_cfg,
|
||||
&dra7xx_l3_main_1__l4_per1,
|
||||
&dra7xx_l3_main_1__l4_per2,
|
||||
&dra7xx_l3_main_1__l4_per3,
|
||||
&dra7xx_l3_main_1__l4_wkup,
|
||||
&dra7xx_l4_per2__atl,
|
||||
&dra7xx_l3_main_1__bb2d,
|
||||
&dra7xx_l4_wkup__ctrl_module_wkup,
|
||||
&dra7xx_l4_cfg__mpu,
|
||||
&dra7xx_l3_main_1__pciess1,
|
||||
&dra7xx_l4_cfg__pciess1,
|
||||
&dra7xx_l3_main_1__pciess2,
|
||||
&dra7xx_l4_cfg__pciess2,
|
||||
&dra7xx_l3_main_1__qspi,
|
||||
&dra7xx_l4_cfg__sata,
|
||||
&dra7xx_l3_main_1__vcp1,
|
||||
&dra7xx_l4_per2__vcp1,
|
||||
&dra7xx_l3_main_1__vcp2,
|
||||
&dra7xx_l4_per2__vcp2,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/* SoC variant specific hwmod links */
|
||||
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init dra7xx_hwmod_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
omap_hwmod_init();
|
||||
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
||||
|
||||
if (!ret && soc_is_dra74x()) {
|
||||
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
||||
} else if (!ret && soc_is_dra72x()) {
|
||||
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
|
||||
if (!ret && !of_machine_is_compatible("ti,dra718"))
|
||||
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
||||
} else if (!ret && soc_is_dra76x()) {
|
||||
if (!ret && soc_is_dra76x_abz())
|
||||
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -443,7 +443,7 @@ void omap_auxdata_legacy_init(struct device *dev)
|
||||
dev->platform_data = &twl_gpio_auxdata;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_OMAP_MCBSP)
|
||||
#if defined(CONFIG_ARCH_OMAP3) && IS_ENABLED(CONFIG_SND_SOC_OMAP_MCBSP)
|
||||
static struct omap_mcbsp_platform_data mcbsp_pdata;
|
||||
static void __init omap3_mcbsp_init(void)
|
||||
{
|
||||
@ -569,10 +569,29 @@ static void pdata_quirks_check(struct pdata_init *quirks)
|
||||
}
|
||||
}
|
||||
|
||||
void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
|
||||
static const char * const pdata_quirks_init_nodes[] = {
|
||||
"prcm",
|
||||
"prm",
|
||||
};
|
||||
|
||||
void __init
|
||||
pdata_quirks_init_clocks(const struct of_device_id *omap_dt_match_table)
|
||||
{
|
||||
struct device_node *np;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pdata_quirks_init_nodes); i++) {
|
||||
np = of_find_node_by_name(NULL, pdata_quirks_init_nodes[i]);
|
||||
if (!np)
|
||||
continue;
|
||||
|
||||
of_platform_populate(np, omap_dt_match_table,
|
||||
omap_auxdata_lookup, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
|
||||
{
|
||||
/*
|
||||
* We still need this for omap2420 and omap3 PM to work, others are
|
||||
* using drivers/misc/sram.c already.
|
||||
@ -585,13 +604,7 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
|
||||
omap3_mcbsp_init();
|
||||
pdata_quirks_check(auxdata_quirks);
|
||||
|
||||
/* Populate always-on PRCM in l4_wkup to probe l4_wkup */
|
||||
np = of_find_node_by_name(NULL, "prcm");
|
||||
if (!np)
|
||||
np = of_find_node_by_name(NULL, "prm");
|
||||
if (np)
|
||||
of_platform_populate(np, omap_dt_match_table,
|
||||
omap_auxdata_lookup, NULL);
|
||||
pdata_quirks_init_clocks(omap_dt_match_table);
|
||||
|
||||
of_platform_populate(NULL, omap_dt_match_table,
|
||||
omap_auxdata_lookup, NULL);
|
||||
|
||||
@ -88,34 +88,26 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
|
||||
|
||||
extern struct omap_sr_data omap_sr_pdata[];
|
||||
|
||||
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
static int __init sr_init_by_name(const char *name, const char *voltdm)
|
||||
{
|
||||
struct omap_sr_data *sr_data = NULL;
|
||||
struct omap_volt_data *volt_data;
|
||||
struct omap_smartreflex_dev_attr *sr_dev_attr;
|
||||
static int i;
|
||||
|
||||
if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
|
||||
!strncmp(oh->name, "smartreflex_mpu", 16))
|
||||
if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
|
||||
!strncmp(name, "smartreflex_mpu", 16))
|
||||
sr_data = &omap_sr_pdata[OMAP_SR_MPU];
|
||||
else if (!strncmp(oh->name, "smartreflex_core", 17))
|
||||
else if (!strncmp(name, "smartreflex_core", 17))
|
||||
sr_data = &omap_sr_pdata[OMAP_SR_CORE];
|
||||
else if (!strncmp(oh->name, "smartreflex_iva", 16))
|
||||
else if (!strncmp(name, "smartreflex_iva", 16))
|
||||
sr_data = &omap_sr_pdata[OMAP_SR_IVA];
|
||||
|
||||
if (!sr_data) {
|
||||
pr_err("%s: Unknown instance %s\n", __func__, oh->name);
|
||||
pr_err("%s: Unknown instance %s\n", __func__, name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
|
||||
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
|
||||
pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
|
||||
__func__, oh->name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
sr_data->name = oh->name;
|
||||
sr_data->name = name;
|
||||
if (cpu_is_omap343x())
|
||||
sr_data->ip_type = 1;
|
||||
else
|
||||
@ -136,10 +128,10 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
}
|
||||
}
|
||||
|
||||
sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
|
||||
sr_data->voltdm = voltdm_lookup(voltdm);
|
||||
if (!sr_data->voltdm) {
|
||||
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
|
||||
__func__, sr_dev_attr->sensor_voltdm_name);
|
||||
__func__, voltdm);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
@ -160,6 +152,27 @@ exit:
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
{
|
||||
struct omap_smartreflex_dev_attr *sr_dev_attr;
|
||||
|
||||
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
|
||||
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
|
||||
pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
|
||||
__func__, oh->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
|
||||
}
|
||||
#else
|
||||
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* API to be called from board files to enable smartreflex
|
||||
* autocompensation at init.
|
||||
@ -169,7 +182,42 @@ void __init omap_enable_smartreflex_on_init(void)
|
||||
sr_enable_on_init = true;
|
||||
}
|
||||
|
||||
static const char * const omap4_sr_instances[] = {
|
||||
"mpu",
|
||||
"iva",
|
||||
"core",
|
||||
};
|
||||
|
||||
static const char * const dra7_sr_instances[] = {
|
||||
"mpu",
|
||||
"core",
|
||||
};
|
||||
|
||||
int __init omap_devinit_smartreflex(void)
|
||||
{
|
||||
const char * const *sr_inst;
|
||||
int i, nr_sr = 0;
|
||||
|
||||
if (soc_is_omap44xx()) {
|
||||
sr_inst = omap4_sr_instances;
|
||||
nr_sr = ARRAY_SIZE(omap4_sr_instances);
|
||||
|
||||
} else if (soc_is_dra7xx()) {
|
||||
sr_inst = dra7_sr_instances;
|
||||
nr_sr = ARRAY_SIZE(dra7_sr_instances);
|
||||
}
|
||||
|
||||
if (nr_sr) {
|
||||
const char *name, *voltdm;
|
||||
|
||||
for (i = 0; i < nr_sr; i++) {
|
||||
name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
|
||||
voltdm = sr_inst[i];
|
||||
sr_init_by_name(name, voltdm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
|
||||
}
|
||||
|
||||
@ -285,7 +285,7 @@ static int omap_l3_probe(struct platform_device *pdev)
|
||||
*/
|
||||
l3->debug_irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
|
||||
0x0, "l3-dbg-irq", l3);
|
||||
IRQF_NO_THREAD, "l3-dbg-irq", l3);
|
||||
if (ret) {
|
||||
dev_err(l3->dev, "request_irq failed for %d\n",
|
||||
l3->debug_irq);
|
||||
@ -294,7 +294,7 @@ static int omap_l3_probe(struct platform_device *pdev)
|
||||
|
||||
l3->app_irq = platform_get_irq(pdev, 1);
|
||||
ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
|
||||
0x0, "l3-app-irq", l3);
|
||||
IRQF_NO_THREAD, "l3-app-irq", l3);
|
||||
if (ret)
|
||||
dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
|
||||
|
||||
|
||||
@ -635,6 +635,51 @@ static int sysc_parse_and_check_child_range(struct sysc *ddata)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Interconnect instances to probe before l4_per instances */
|
||||
static struct resource early_bus_ranges[] = {
|
||||
/* am3/4 l4_wkup */
|
||||
{ .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
|
||||
/* omap4/5 and dra7 l4_cfg */
|
||||
{ .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
|
||||
/* omap4 l4_wkup */
|
||||
{ .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
|
||||
/* omap5 and dra7 l4_wkup without dra7 dcan segment */
|
||||
{ .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
|
||||
};
|
||||
|
||||
static atomic_t sysc_defer = ATOMIC_INIT(10);
|
||||
|
||||
/**
|
||||
* sysc_defer_non_critical - defer non_critical interconnect probing
|
||||
* @ddata: device driver data
|
||||
*
|
||||
* We want to probe l4_cfg and l4_wkup interconnect instances before any
|
||||
* l4_per instances as l4_per instances depend on resources on l4_cfg and
|
||||
* l4_wkup interconnects.
|
||||
*/
|
||||
static int sysc_defer_non_critical(struct sysc *ddata)
|
||||
{
|
||||
struct resource *res;
|
||||
int i;
|
||||
|
||||
if (!atomic_read(&sysc_defer))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
|
||||
res = &early_bus_ranges[i];
|
||||
if (ddata->module_pa >= res->start &&
|
||||
ddata->module_pa <= res->end) {
|
||||
atomic_set(&sysc_defer, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
atomic_dec_if_positive(&sysc_defer);
|
||||
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
static struct device_node *stdout_path;
|
||||
|
||||
static void sysc_init_stdout_path(struct sysc *ddata)
|
||||
@ -856,15 +901,19 @@ static int sysc_map_and_check_registers(struct sysc *ddata)
|
||||
struct device_node *np = ddata->dev->of_node;
|
||||
int error;
|
||||
|
||||
if (!of_get_property(np, "reg", NULL))
|
||||
return 0;
|
||||
|
||||
error = sysc_parse_and_check_child_range(ddata);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = sysc_defer_non_critical(ddata);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
sysc_check_children(ddata);
|
||||
|
||||
if (!of_get_property(np, "reg", NULL))
|
||||
return 0;
|
||||
|
||||
error = sysc_parse_registers(ddata);
|
||||
if (error)
|
||||
return error;
|
||||
@ -1447,12 +1496,16 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
|
||||
SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
|
||||
SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
|
||||
SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
|
||||
SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
|
||||
SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
|
||||
SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
|
||||
SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
|
||||
SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
|
||||
SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
|
||||
SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
|
||||
SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
|
||||
SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
|
||||
SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
|
||||
SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
|
||||
SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
|
||||
SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
|
||||
@ -1464,11 +1517,14 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
|
||||
SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
|
||||
SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
|
||||
SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
|
||||
SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
|
||||
SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
|
||||
SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
|
||||
SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
|
||||
SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
|
||||
SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
|
||||
SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
|
||||
SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 0),
|
||||
SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
|
||||
SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
|
||||
SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
|
||||
@ -2802,6 +2858,7 @@ static int sysc_init_soc(struct sysc *ddata)
|
||||
const struct soc_device_attribute *match;
|
||||
struct ti_sysc_platform_data *pdata;
|
||||
unsigned long features = 0;
|
||||
struct device_node *np;
|
||||
|
||||
if (sysc_soc)
|
||||
return 0;
|
||||
@ -2822,6 +2879,24 @@ static int sysc_init_soc(struct sysc *ddata)
|
||||
if (match && match->data)
|
||||
sysc_soc->soc = (int)match->data;
|
||||
|
||||
/*
|
||||
* Check and warn about possible old incomplete dtb. We now want to see
|
||||
* simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
|
||||
*/
|
||||
switch (sysc_soc->soc) {
|
||||
case SOC_AM3:
|
||||
case SOC_AM4:
|
||||
case SOC_4430 ... SOC_4470:
|
||||
case SOC_5430:
|
||||
case SOC_DRA7:
|
||||
np = of_find_node_by_path("/ocp");
|
||||
WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
|
||||
"ti-sysc: Incomplete old dtb, please update\n");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Ignore devices that are not available on HS and EMU SoCs */
|
||||
if (!sysc_soc->general_purpose) {
|
||||
switch (sysc_soc->soc) {
|
||||
@ -3053,7 +3128,9 @@ static int sysc_remove(struct platform_device *pdev)
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
reset_control_assert(ddata->rsts);
|
||||
|
||||
if (!reset_control_status(ddata->rsts))
|
||||
reset_control_assert(ddata->rsts);
|
||||
|
||||
unprepare:
|
||||
sysc_unprepare(ddata);
|
||||
|
||||
@ -156,6 +156,8 @@ static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initcon
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
|
||||
{ OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
|
||||
{ OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
||||
@ -443,8 +443,8 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = {
|
||||
.get_features = dra7xx_pcie_get_features,
|
||||
};
|
||||
|
||||
static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
|
||||
struct platform_device *pdev)
|
||||
static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct dw_pcie_ep *ep;
|
||||
@ -472,8 +472,8 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
|
||||
struct platform_device *pdev)
|
||||
static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct dw_pcie *pci = dra7xx->pci;
|
||||
@ -682,7 +682,7 @@ static int dra7xx_pcie_configure_two_lane(struct device *dev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
|
||||
static int dra7xx_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
u32 reg;
|
||||
int ret;
|
||||
@ -938,6 +938,7 @@ static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
|
||||
};
|
||||
|
||||
static struct platform_driver dra7xx_pcie_driver = {
|
||||
.probe = dra7xx_pcie_probe,
|
||||
.driver = {
|
||||
.name = "dra7-pcie",
|
||||
.of_match_table = of_dra7xx_pcie_match,
|
||||
@ -946,4 +947,4 @@ static struct platform_driver dra7xx_pcie_driver = {
|
||||
},
|
||||
.shutdown = dra7xx_pcie_shutdown,
|
||||
};
|
||||
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
|
||||
builtin_platform_driver(dra7xx_pcie_driver);
|
||||
|
||||
@ -88,6 +88,7 @@ struct omap_reset_data {
|
||||
#define OMAP_PRM_HAS_RSTCTRL BIT(0)
|
||||
#define OMAP_PRM_HAS_RSTST BIT(1)
|
||||
#define OMAP_PRM_HAS_NO_CLKDM BIT(2)
|
||||
#define OMAP_PRM_RET_WHEN_IDLE BIT(3)
|
||||
|
||||
#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST)
|
||||
|
||||
@ -174,7 +175,8 @@ static const struct omap_prm_data omap4_prm_data[] = {
|
||||
.name = "core", .base = 0x4a306700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
|
||||
.rstmap = rst_map_012
|
||||
.rstmap = rst_map_012,
|
||||
.flags = OMAP_PRM_RET_WHEN_IDLE,
|
||||
},
|
||||
{
|
||||
.name = "ivahd", .base = 0x4a306f00,
|
||||
@ -199,7 +201,8 @@ static const struct omap_prm_data omap4_prm_data[] = {
|
||||
},
|
||||
{
|
||||
.name = "l4per", .base = 0x4a307400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
.flags = OMAP_PRM_RET_WHEN_IDLE,
|
||||
},
|
||||
{
|
||||
.name = "cefuse", .base = 0x4a307600,
|
||||
@ -332,7 +335,7 @@ static const struct omap_prm_data dra7_prm_data[] = {
|
||||
{
|
||||
.name = "l3init", .base = 0x4ae07300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
|
||||
.clkdm_name = "pcie"
|
||||
},
|
||||
{
|
||||
@ -517,7 +520,7 @@ static int omap_prm_domain_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct omap_prm_domain *prmd;
|
||||
int ret;
|
||||
u32 v;
|
||||
u32 v, mode;
|
||||
|
||||
prmd = genpd_to_prm_domain(domain);
|
||||
if (!prmd->cap)
|
||||
@ -530,7 +533,12 @@ static int omap_prm_domain_power_on(struct generic_pm_domain *domain)
|
||||
else
|
||||
v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
|
||||
|
||||
writel_relaxed(v | OMAP_PRMD_ON_ACTIVE,
|
||||
if (prmd->prm->data->flags & OMAP_PRM_RET_WHEN_IDLE)
|
||||
mode = OMAP_PRMD_RETENTION;
|
||||
else
|
||||
mode = OMAP_PRMD_ON_ACTIVE;
|
||||
|
||||
writel_relaxed((v & ~PRM_POWERSTATE_MASK) | mode,
|
||||
prmd->prm->base + prmd->pwrstctrl);
|
||||
|
||||
/* wait for the transition bit to get cleared */
|
||||
@ -830,8 +838,12 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
reset->prm->data->name, id);
|
||||
|
||||
exit:
|
||||
if (reset->clkdm)
|
||||
if (reset->clkdm) {
|
||||
/* At least dra7 iva needs a delay before clkdm idle */
|
||||
if (has_rstst)
|
||||
udelay(1);
|
||||
pdata->clkdm_allow_idle(reset->clkdm);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -32,6 +32,8 @@
|
||||
|
||||
/* l3main2 clocks */
|
||||
#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
|
||||
/* ipu clocks */
|
||||
#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user