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x86/CPU/AMD: Add X86_FEATURE_ZEN5

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Add a synthetic feature flag for Zen5.

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20240104201138.5072-1-bp@alien8.de
This commit is contained in:
Borislav Petkov (AMD) 2024-01-04 21:11:37 +01:00
parent f7cfe7017b
commit 3e4147f33f
2 changed files with 22 additions and 7 deletions
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4
arch/x86/include/asm/cpufeatures.h
View File

@ -81,10 +81,8 @@
#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* CPU types for specific tunings: */
#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */
#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */

25
arch/x86/kernel/cpu/amd.c
View File

@ -538,7 +538,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
/* Figure out Zen generations: */ /* Figure out Zen generations: */
switch (c->x86) { switch (c->x86) {
case 0x17: { case 0x17:
switch (c->x86_model) { switch (c->x86_model) {
case 0x00 ... 0x2f: case 0x00 ... 0x2f:
case 0x50 ... 0x5f: case 0x50 ... 0x5f:
@ -554,8 +554,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
goto warn; goto warn;
} }
break; break;
}
case 0x19: { case 0x19:
switch (c->x86_model) { switch (c->x86_model) {
case 0x00 ... 0x0f: case 0x00 ... 0x0f:
case 0x20 ... 0x5f: case 0x20 ... 0x5f:
@ -569,7 +569,17 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
goto warn; goto warn;
} }
break; break;
}
case 0x1a:
switch (c->x86_model) {
case 0x00 ... 0x0f:
setup_force_cpu_cap(X86_FEATURE_ZEN5);
break;
default:
goto warn;
}
break;
default: default:
break; break;
} }
@ -1039,6 +1049,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c)
msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
} }
static void init_amd_zen5(struct cpuinfo_x86 *c)
{
init_amd_zen_common();
}
static void init_amd(struct cpuinfo_x86 *c) static void init_amd(struct cpuinfo_x86 *c)
{ {
u64 vm_cr; u64 vm_cr;
@ -1084,6 +1099,8 @@ static void init_amd(struct cpuinfo_x86 *c)
init_amd_zen3(c); init_amd_zen3(c);
else if (boot_cpu_has(X86_FEATURE_ZEN4)) else if (boot_cpu_has(X86_FEATURE_ZEN4))
init_amd_zen4(c); init_amd_zen4(c);
else if (boot_cpu_has(X86_FEATURE_ZEN5))
init_amd_zen5(c);
/* /*
* Enable workaround for FXSAVE leak on CPUs * Enable workaround for FXSAVE leak on CPUs