[ARM] msm: irq and timer support for ARCH_MSM7X00A
- Vectored Interrupt Controller support - Timer support using the GPT and DGT timers Signed-off-by: Brian Swetland <swetland@google.com>
This commit is contained in:
Arve Hjønnevåg
Russell King
parent
3042102a28
commit
3e4ea3728a
@ -1,2 +1,2 @@
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obj-y += io.o idle.o
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obj-y += io.o idle.o irq.o timer.o
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154
arch/arm/mach-msm/irq.c
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154
arch/arm/mach-msm/irq.c
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/* linux/arch/arm/mach-msm/irq.c
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*
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/msm_iomap.h>
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#define VIC_REG(off) (MSM_VIC_BASE + (off))
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#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_EN0 VIC_REG(0x0010)
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#define VIC_INT_EN1 VIC_REG(0x0014)
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#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
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#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
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#define VIC_INT_ENSET0 VIC_REG(0x0030)
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#define VIC_INT_ENSET1 VIC_REG(0x0034)
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#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
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#define VIC_NO_PEND_VAL VIC_REG(0x0060)
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#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
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#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
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#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
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#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
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#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
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#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
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#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
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#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
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#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
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#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
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#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
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#define VIC_SOFTINT0 VIC_REG(0x00C0)
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#define VIC_SOFTINT1 VIC_REG(0x00C4)
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#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
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#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
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#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
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#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
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#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
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static void msm_irq_ack(unsigned int irq)
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{
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unsigned reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
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irq = 1 << (irq & 31);
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writel(irq, reg);
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}
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static void msm_irq_mask(unsigned int irq)
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{
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unsigned reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
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writel(1 << (irq & 31), reg);
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}
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static void msm_irq_unmask(unsigned int irq)
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{
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unsigned reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
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writel(1 << (irq & 31), reg);
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}
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static int msm_irq_set_wake(unsigned int irq, unsigned int on)
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{
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return -EINVAL;
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}
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static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
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unsigned preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
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int b = 1 << (irq & 31);
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if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
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writel(readl(preg) | b, preg);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
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writel(readl(preg) & (~b), preg);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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writel(readl(treg) | b, treg);
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set_irq_handler(irq, handle_edge_irq);
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}
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if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
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writel(readl(treg) & (~b), treg);
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set_irq_handler(irq, handle_level_irq);
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}
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return 0;
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}
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static struct irq_chip msm_irq_chip = {
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.name = "msm",
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.ack = msm_irq_ack,
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.mask = msm_irq_mask,
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.unmask = msm_irq_unmask,
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.set_wake = msm_irq_set_wake,
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.set_type = msm_irq_set_type,
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};
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void __init msm_init_irq(void)
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{
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unsigned n;
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/* select level interrupts */
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writel(0, VIC_INT_TYPE0);
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writel(0, VIC_INT_TYPE1);
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/* select highlevel interrupts */
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writel(0, VIC_INT_POLARITY0);
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writel(0, VIC_INT_POLARITY1);
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/* select IRQ for all INTs */
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writel(0, VIC_INT_SELECT0);
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writel(0, VIC_INT_SELECT1);
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/* disable all INTs */
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writel(0, VIC_INT_EN0);
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writel(0, VIC_INT_EN1);
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/* don't use 1136 vic */
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writel(0, VIC_CONFIG);
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/* enable interrupt controller */
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writel(1, VIC_INT_MASTEREN);
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for (n = 0; n < NR_MSM_IRQS; n++) {
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set_irq_chip(n, &msm_irq_chip);
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set_irq_handler(n, handle_level_irq);
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set_irq_flags(n, IRQF_VALID);
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}
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}
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205
arch/arm/mach-msm/timer.c
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205
arch/arm/mach-msm/timer.c
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@ -0,0 +1,205 @@
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/* linux/arch/arm/mach-msm/timer.c
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*
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <asm/mach/time.h>
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#include <asm/arch/msm_iomap.h>
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#include <asm/io.h>
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#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
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#define MSM_DGT_SHIFT (5)
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
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#define TIMER_ENABLE_EN 1
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#define TIMER_CLEAR 0x000C
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#define CSR_PROTECTION 0x0020
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#define CSR_PROTECTION_EN 1
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#define GPT_HZ 32768
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#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
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struct msm_clock {
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struct clock_event_device clockevent;
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struct clocksource clocksource;
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struct irqaction irq;
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uint32_t regbase;
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uint32_t freq;
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uint32_t shift;
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};
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static cycle_t msm_gpt_read(void)
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{
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return readl(MSM_GPT_BASE + TIMER_COUNT_VAL);
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}
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static cycle_t msm_dgt_read(void)
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{
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return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
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}
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static int msm_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
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uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL);
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uint32_t alarm = now + (cycles << clock->shift);
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int late;
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writel(alarm, clock->regbase + TIMER_MATCH_VAL);
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now = readl(clock->regbase + TIMER_COUNT_VAL);
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late = now - alarm;
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if (late >= (-2 << clock->shift) && late < DGT_HZ*5) {
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printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, "
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"alarm already expired, now %x, alarm %x, late %d\n",
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cycles, clock->clockevent.name, now, alarm, late);
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return -ETIME;
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}
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return 0;
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}
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static void msm_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel(0, clock->regbase + TIMER_ENABLE);
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break;
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}
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}
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static struct msm_clock msm_clocks[] = {
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{
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.clockevent = {
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.name = "gp_timer",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 200,
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.set_next_event = msm_timer_set_next_event,
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.set_mode = msm_timer_set_mode,
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},
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.clocksource = {
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.name = "gp_timer",
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.rating = 200,
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.read = msm_gpt_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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.irq = {
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.name = "gp_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
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.handler = msm_timer_interrupt,
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.dev_id = &msm_clocks[0].clockevent,
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.irq = INT_GP_TIMER_EXP
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},
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.regbase = MSM_GPT_BASE,
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.freq = GPT_HZ
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},
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{
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.clockevent = {
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.name = "dg_timer",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32 + MSM_DGT_SHIFT,
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.rating = 300,
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.set_next_event = msm_timer_set_next_event,
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.set_mode = msm_timer_set_mode,
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},
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.clocksource = {
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.name = "dg_timer",
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.rating = 300,
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.read = msm_dgt_read,
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.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
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.shift = 24 - MSM_DGT_SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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.irq = {
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.name = "dg_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
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.handler = msm_timer_interrupt,
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.dev_id = &msm_clocks[1].clockevent,
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.irq = INT_DEBUG_TIMER_EXP
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},
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.regbase = MSM_DGT_BASE,
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.freq = DGT_HZ >> MSM_DGT_SHIFT,
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.shift = MSM_DGT_SHIFT
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}
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};
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static void __init msm_timer_init(void)
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{
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int i;
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int res;
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for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
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struct msm_clock *clock = &msm_clocks[i];
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struct clock_event_device *ce = &clock->clockevent;
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struct clocksource *cs = &clock->clocksource;
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writel(0, clock->regbase + TIMER_ENABLE);
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writel(0, clock->regbase + TIMER_CLEAR);
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writel(~0, clock->regbase + TIMER_MATCH_VAL);
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ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
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/* allow at least 10 seconds to notice that the timer wrapped */
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ce->max_delta_ns =
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clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
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/* 4 gets rounded down to 3 */
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ce->min_delta_ns = clockevent_delta2ns(4, ce);
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ce->cpumask = cpumask_of_cpu(0);
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cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
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res = clocksource_register(cs);
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if (res)
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printk(KERN_ERR "msm_timer_init: clocksource_register "
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"failed for %s\n", cs->name);
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res = setup_irq(clock->irq.irq, &clock->irq);
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if (res)
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printk(KERN_ERR "msm_timer_init: setup_irq "
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"failed for %s\n", cs->name);
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clockevents_register_device(ce);
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}
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}
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struct sys_timer msm_timer = {
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.init = msm_timer_init
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};
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