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ARM: OMAP: move plat-omap/include/plat/sdrc.h into mach-omap2/sdrc.h

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Remove arch/arm/plat-omap/include/plat/sdrc.h by folding its contents
into arch/arm/mach-omap2/sdrc.h.  The objective is to assist Tony in
cleaning out arch/arm/plat-omap/, as his upstreams request.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
[tony@atomide.com: updated to remove rotate macros]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Paul Walmsley 2012-10-17 00:46:45 +00:00 committed by Tony Lindgren
parent 1d81aea146
commit 3e6ece13d9
17 changed files with 149 additions and 180 deletions
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1
arch/arm/mach-omap2/board-omap3logic.c
View File

@ -36,7 +36,6 @@
#include "gpmc-smsc911x.h"
#include <plat/gpmc.h>
#include <plat/sdrc.h>
#include <plat/usb.h>
#include "common.h"

2
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View File

@ -27,13 +27,13 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */

2
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@ -35,7 +35,6 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include "soc.h"
#include "clock.h"
@ -43,6 +42,7 @@
#include "opp2xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;

1
arch/arm/mach-omap2/clkt34xx_dpll3m2.c
View File

@ -23,7 +23,6 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include "clock.h"
#include "clock3xxx.h"

4
arch/arm/mach-omap2/control.c
View File

@ -1,7 +1,7 @@
/*
* OMAP2/3 System Control Module register access
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Copyright (C) 2007, 2012 Texas Instruments, Inc.
* Copyright (C) 2007 Nokia Corporation
*
* Written by Paul Walmsley
@ -15,8 +15,6 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <plat/sdrc.h>
#include "soc.h"
#include "iomap.h"
#include "common.h"

1
arch/arm/mach-omap2/gpmc.c
View File

@ -31,7 +31,6 @@
#include <plat/cpu.h>
#include <plat/gpmc.h>
#include <plat/sdrc.h>
#include <plat/omap_device.h>
#include "soc.h"

2
arch/arm/mach-omap2/io.c
View File

@ -26,7 +26,6 @@
#include <asm/mach/map.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/serial.h>
#include <plat/omap-pm.h>
#include <plat/omap_hwmod.h>
@ -43,6 +42,7 @@
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "clock44xx.h"
#include "sdrc.h"
/*
* The machine specific code may provide the extra mapping besides the

1
arch/arm/mach-omap2/pm34xx.c
View File

@ -38,7 +38,6 @@
#include <plat/sram.h>
#include "clockdomain.h"
#include "powerdomain.h"
#include <plat/sdrc.h>
#include <plat/prcm.h>
#include <plat/gpmc.h>
#include <plat/dma.h>

2
arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
View File

@ -11,7 +11,7 @@
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#include <plat/sdrc.h>
#include "sdrc.h"
/* Hynix H8MBX00U0MER-0EM */
static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {

2
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
View File

@ -14,7 +14,7 @@
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#include <plat/sdrc.h>
#include "sdrc.h"
/* Micron MT46H32M32LF-6 */
/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */

2
arch/arm/mach-omap2/sdram-nokia.c
View File

@ -19,9 +19,9 @@
#include "common.h"
#include <plat/clock.h>
#include <plat/sdrc.h>
#include "sdram-nokia.h"
#include "sdrc.h"
/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
struct sdram_timings {

2
arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
View File

@ -11,7 +11,7 @@
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#include <plat/sdrc.h>
#include "sdrc.h"
/* Numonyx M65KXXXXAM */
static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {

2
arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
View File

@ -14,7 +14,7 @@
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#include <plat/sdrc.h>
#include "sdrc.h"
/* Qimonda HYB18M512160AF-6 */
static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {

1
arch/arm/mach-omap2/sdrc.c
View File

@ -27,7 +27,6 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include "sdrc.h"
static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;

146
arch/arm/mach-omap2/sdrc.h
View File

@ -2,12 +2,14 @@
#define __ARCH_ARM_MACH_OMAP2_SDRC_H
/*
* OMAP2 SDRC register definitions
* OMAP2/3 SDRC/SMS macros and prototypes
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Copyright (C) 2007 Nokia Corporation
* Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
* Paul Walmsley
* Tony Lindgren
* Richard Woodruff
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -15,8 +17,6 @@
*/
#undef DEBUG
#include <plat/sdrc.h>
#ifndef __ASSEMBLER__
#include <linux/io.h>
@ -50,6 +50,58 @@ static inline u32 sms_read_reg(u16 reg)
{
return __raw_readl(OMAP_SMS_REGADDR(reg));
}
/**
* struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
* @rate: SDRC clock rate (in Hz)
* @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
* @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
* @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
* @mr: Value to program to SDRC_MR for this rate
*
* This structure holds a pre-computed set of register values for the
* SDRC for a given SDRC clock rate and SDRAM chip. These are
* intended to be pre-computed and specified in an array in the board-*.c
* files. The structure is keyed off the 'rate' field.
*/
struct omap_sdrc_params {
unsigned long rate;
u32 actim_ctrla;
u32 actim_ctrlb;
u32 rfr_ctrl;
u32 mr;
};
#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
#else
static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1) {};
#endif
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
void omap2_sms_save_context(void);
void omap2_sms_restore_context(void);
struct memory_timings {
u32 m_type; /* ddr = 1, sdr = 0 */
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
u32 base_cs; /* base chip select to use for calculations */
};
extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
struct omap_sdrc_params *rx51_get_sdram_timings(void);
u32 omap2xxx_sdrc_dll_is_unlocked(void);
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
#else
#define OMAP242X_SDRC_REGADDR(reg) \
OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
@ -57,6 +109,7 @@ static inline u32 sms_read_reg(u16 reg)
OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
#define OMAP34XX_SDRC_REGADDR(reg) \
OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
#endif /* __ASSEMBLER__ */
/* Minimum frequency that the SDRC DLL can lock at */
@ -74,4 +127,85 @@ static inline u32 sms_read_reg(u16 reg)
*/
#define SDRC_MPURATE_LOOPS 96
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
#define SDRC_SYSCONFIG 0x010
#define SDRC_CS_CFG 0x040
#define SDRC_SHARING 0x044
#define SDRC_ERR_TYPE 0x04C
#define SDRC_DLLA_CTRL 0x060
#define SDRC_DLLA_STATUS 0x064
#define SDRC_DLLB_CTRL 0x068
#define SDRC_DLLB_STATUS 0x06C
#define SDRC_POWER 0x070
#define SDRC_MCFG_0 0x080
#define SDRC_MR_0 0x084
#define SDRC_EMR2_0 0x08c
#define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4
#define SDRC_MANUAL_0 0x0a8
#define SDRC_MCFG_1 0x0B0
#define SDRC_MR_1 0x0B4
#define SDRC_EMR2_1 0x0BC
#define SDRC_ACTIM_CTRL_A_1 0x0C4
#define SDRC_ACTIM_CTRL_B_1 0x0C8
#define SDRC_RFR_CTRL_1 0x0D4
#define SDRC_MANUAL_1 0x0D8
#define SDRC_POWER_AUTOCOUNT_SHIFT 8
#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
#define SDRC_POWER_CLKCTRL_SHIFT 4
#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
/*
* These values represent the number of memory clock cycles between
* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
* rows per device, and include a subtraction of a 50 cycle window in the
* event that the autorefresh command is delayed due to other SDRC activity.
* The '| 1' sets the ARE field to send one autorefresh when the autorefresh
* counter reaches 0.
*
* These represent optimal values for common parts, it won't work for all.
* As long as you scale down, most parameters are still work, they just
* become sub-optimal. The RFR value goes in the opposite direction. If you
* don't adjust it down as your clock period increases the refresh interval
* will not be met. Setting all parameters for complete worst case may work,
* but may cut memory performance by 2x. Due to errata the DLLs need to be
* unlocked and their value needs run time calibration. A dynamic call is
* need for that as no single right value exists acorss production samples.
*
* Only the FULL speed values are given. Current code is such that rate
* changes must be made at DPLLoutx2. The actual value adjustment for low
* frequency operation will be handled by omap_set_performance()
*
* By having the boot loader boot up in the fastest L4 speed available likely
* will result in something which you can switch between.
*/
#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
/*
* SMS register access
*/
#define OMAP242X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
#define OMAP243X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
#define OMAP343X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
/* SMS register offsets - read/write with sms_{read,write}_reg() */
#define SMS_SYSCONFIG 0x010
/* REVISIT: fill in other SMS registers here */
#endif

1
arch/arm/mach-omap2/sdrc2xxx.c
View File

@ -26,7 +26,6 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include "soc.h"
#include "iomap.h"

157
arch/arm/plat-omap/include/plat/sdrc.h
View File

@ -1,157 +0,0 @@
#ifndef ____ASM_ARCH_SDRC_H
#define ____ASM_ARCH_SDRC_H
/*
* OMAP2/3 SDRC/SMS register definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Tony Lindgren
* Paul Walmsley
* Richard Woodruff
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
#define SDRC_SYSCONFIG 0x010
#define SDRC_CS_CFG 0x040
#define SDRC_SHARING 0x044
#define SDRC_ERR_TYPE 0x04C
#define SDRC_DLLA_CTRL 0x060
#define SDRC_DLLA_STATUS 0x064
#define SDRC_DLLB_CTRL 0x068
#define SDRC_DLLB_STATUS 0x06C
#define SDRC_POWER 0x070
#define SDRC_MCFG_0 0x080
#define SDRC_MR_0 0x084
#define SDRC_EMR2_0 0x08c
#define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4
#define SDRC_MANUAL_0 0x0a8
#define SDRC_MCFG_1 0x0B0
#define SDRC_MR_1 0x0B4
#define SDRC_EMR2_1 0x0BC
#define SDRC_ACTIM_CTRL_A_1 0x0C4
#define SDRC_ACTIM_CTRL_B_1 0x0C8
#define SDRC_RFR_CTRL_1 0x0D4
#define SDRC_MANUAL_1 0x0D8
#define SDRC_POWER_AUTOCOUNT_SHIFT 8
#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
#define SDRC_POWER_CLKCTRL_SHIFT 4
#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
/*
* These values represent the number of memory clock cycles between
* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
* rows per device, and include a subtraction of a 50 cycle window in the
* event that the autorefresh command is delayed due to other SDRC activity.
* The '| 1' sets the ARE field to send one autorefresh when the autorefresh
* counter reaches 0.
*
* These represent optimal values for common parts, it won't work for all.
* As long as you scale down, most parameters are still work, they just
* become sub-optimal. The RFR value goes in the opposite direction. If you
* don't adjust it down as your clock period increases the refresh interval
* will not be met. Setting all parameters for complete worst case may work,
* but may cut memory performance by 2x. Due to errata the DLLs need to be
* unlocked and their value needs run time calibration. A dynamic call is
* need for that as no single right value exists acorss production samples.
*
* Only the FULL speed values are given. Current code is such that rate
* changes must be made at DPLLoutx2. The actual value adjustment for low
* frequency operation will be handled by omap_set_performance()
*
* By having the boot loader boot up in the fastest L4 speed available likely
* will result in something which you can switch between.
*/
#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
/*
* SMS register access
*/
#define OMAP242X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
#define OMAP243X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
#define OMAP343X_SMS_REGADDR(reg) \
(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
/* SMS register offsets - read/write with sms_{read,write}_reg() */
#define SMS_SYSCONFIG 0x010
/* REVISIT: fill in other SMS registers here */
#ifndef __ASSEMBLER__
/**
* struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
* @rate: SDRC clock rate (in Hz)
* @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
* @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
* @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
* @mr: Value to program to SDRC_MR for this rate
*
* This structure holds a pre-computed set of register values for the
* SDRC for a given SDRC clock rate and SDRAM chip. These are
* intended to be pre-computed and specified in an array in the board-*.c
* files. The structure is keyed off the 'rate' field.
*/
struct omap_sdrc_params {
unsigned long rate;
u32 actim_ctrla;
u32 actim_ctrlb;
u32 rfr_ctrl;
u32 mr;
};
#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
#else
static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1) {};
#endif
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
void omap2_sms_save_context(void);
void omap2_sms_restore_context(void);
#ifdef CONFIG_ARCH_OMAP2
struct memory_timings {
u32 m_type; /* ddr = 1, sdr = 0 */
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
u32 base_cs; /* base chip select to use for calculations */
};
extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
struct omap_sdrc_params *rx51_get_sdram_timings(void);
u32 omap2xxx_sdrc_dll_is_unlocked(void);
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
#endif /* CONFIG_ARCH_OMAP2 */
#endif /* __ASSEMBLER__ */
#endif