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STM32 DT for v6.10, round 1

Browse Source 
Highlights:
 ----------
 
 - MPU:
   - STM32MP13:
     - Add and enable LTDC display (rocktech,rk043fn48h)
       on stm32mp135f-dk.
     - Add firewall bus based on  ETZPC firewall controller.
     - Add PWR regulator support: Can be only used if the platform is
       set as "no-secure" (RCC_SECCFGR cleared) either use SCMI
       regulator.
 
   - STMP32MP15:
     - Add firewall bus based on  ETZPC firewall controller.
     - Add heartbeat on stm32mp157c-ed1.
 
   - STM32MP25:
     - Add firewall bus based on  RIFSC firewall controller.
     - Add clock support (RCC) based on SCMI clock protocol for root clocks.
     - Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1.
     - Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1.
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Merge tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

STM32 DT for v6.10, round 1

Highlights:
----------

- MPU:
  - STM32MP13:
    - Add and enable LTDC display (rocktech,rk043fn48h)
      on stm32mp135f-dk.
    - Add firewall bus based on  ETZPC firewall controller.
    - Add PWR regulator support: Can be only used if the platform is
      set as "no-secure" (RCC_SECCFGR cleared) either use SCMI
      regulator.

  - STMP32MP15:
    - Add firewall bus based on  ETZPC firewall controller.
    - Add heartbeat on stm32mp157c-ed1.

  - STM32MP25:
    - Add firewall bus based on  RIFSC firewall controller.
    - Add clock support (RCC) based on SCMI clock protocol for root clocks.
    - Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1.
    - Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1.

* tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (21 commits)
  arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25
  arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1
  arm64: dts: st: add spi3/spi8 pins for stm32mp25
  arm64: dts: st: add all 8 spi nodes on stm32mp251
  arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1
  arm64: dts: st: add i2c2/i2c8 pins for stm32mp25
  arm64: dts: st: add all 8 i2c nodes on stm32mp251
  arm64: dts: st: add rcc support for STM32MP25
  ARM: dts: stm32: enable display support on stm32mp135f-dk board
  ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
  ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
  dt-bindings: display: simple: allow panel-common properties
  ARM: dts: stm32: add PWR regulators support on stm32mp131
  media: dt-bindings: add access-controllers to STM32MP25 video codecs
  ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1
  ARM: dts: stm32: move can3 node from stm32f746 to stm32f769
  ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  ...

Link: https://lore.kernel.org/r/2040767c-413e-4447-b354-c44999930e4c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-04-29 10:43:42 +02:00
commit 3f35669158
20 changed files with 2664 additions and 2007 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
View File

@ -348,15 +348,6 @@ properties:
# Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel
- yes-optoelectronics,ytc700tlag-05-201c
backlight: true
ddc-i2c-bus: true
enable-gpios: true
port: true
power-supply: true
no-hpd: true
hpd-gpios: true
data-mapping: true
if:
not:
properties:
@ -367,7 +358,7 @@ then:
properties:
data-mapping: false
additionalProperties: false
unevaluatedProperties: false
required:
- compatible

4
Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml
View File

@ -30,6 +30,10 @@ properties:
clocks:
maxItems: 1
access-controllers:
minItems: 1
maxItems: 2
required:
- compatible
- reg

17
arch/arm/boot/dts/st/stm32f746.dtsi
View File

@ -257,23 +257,6 @@
status = "disabled";
};
can3: can@40003400 {
compatible = "st,stm32f4-bxcan";
reg = <0x40003400 0x200>;
interrupts = <104>, <105>, <106>, <107>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
st,gcan = <&gcan3>;
status = "disabled";
};
gcan3: gcan@40003600 {
compatible = "st,stm32f4-gcan", "syscon";
reg = <0x40003600 0x200>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
spi2: spi@40003800 {
#address-cells = <1>;
#size-cells = <0>;

17
arch/arm/boot/dts/st/stm32f769.dtsi
View File

@ -7,6 +7,23 @@
/ {
soc {
can3: can@40003400 {
compatible = "st,stm32f4-bxcan";
reg = <0x40003400 0x200>;
interrupts = <104>, <105>, <106>, <107>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
st,gcan = <&gcan3>;
status = "disabled";
};
gcan3: gcan@40003600 {
compatible = "st,stm32f4-gcan", "syscon";
reg = <0x40003600 0x200>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;

57
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
View File

@ -47,6 +47,63 @@
};
};
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
<STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
};
};
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;

1088
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

File diff suppressed because it is too large Load Diff

51
arch/arm/boot/dts/st/stm32mp133.dtsi
View File

@ -33,35 +33,38 @@
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
};
};
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
&etzpc {
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&etzpc 32>;
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_1>;
interrupts = <0>;
dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_1>;
interrupts = <0>;
dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
channel@18 {
reg = <18>;
label = "vrefint";
};
channel@18 {
reg = <18>;
label = "vrefint";
};
};
};

11
arch/arm/boot/dts/st/stm32mp135.dtsi
View File

@ -19,5 +19,16 @@
port {
};
};
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LTDC_PX>;
clock-names = "lcd";
resets = <&scmi_reset RST_SCMI_LTDC>;
status = "disabled";
};
};
};

53
arch/arm/boot/dts/st/stm32mp135f-dk.dts
View File

@ -66,6 +66,46 @@
default-state = "off";
};
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
default-on;
status = "okay";
};
panel_rgb: panel-rgb {
compatible = "rocktech,rk043fn48h";
enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
backlight = <&panel_backlight>;
power-supply = <&scmi_v3v3_sw>;
status = "okay";
width-mm = <105>;
height-mm = <67>;
panel-timing {
clock-frequency = <10000000>;
hactive = <480>;
hback-porch = <43>;
hfront-porch = <10>;
hsync-len = <1>;
hsync-active = <0>;
vactive = <272>;
vback-porch = <26>;
vfront-porch = <4>;
vsync-len = <10>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&ltdc_out_rgb>;
};
};
};
};
&adc_1 {
@ -168,6 +208,19 @@
status = "okay";
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_sleep_pins_a>;
status = "okay";
port {
ltdc_out_rgb: endpoint {
remote-endpoint = <&panel_in_rgb>;
};
};
};
&rtc {
status = "okay";
};

19
arch/arm/boot/dts/st/stm32mp13xc.dtsi
View File

@ -4,15 +4,14 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc 42>;
status = "disabled";
};
};

19
arch/arm/boot/dts/st/stm32mp13xf.dtsi
View File

@ -4,15 +4,14 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc 42>;
status = "disabled";
};
};

2726
arch/arm/boot/dts/st/stm32mp151.dtsi
View File

File diff suppressed because it is too large Load Diff

52
arch/arm/boot/dts/st/stm32mp153.dtsi
View File

@ -28,32 +28,34 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
};
&etzpc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";
};
m_can2: can@4400f000 {
compatible = "bosch,m_can";
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
m_can2: can@4400f000 {
compatible = "bosch,m_can";
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";
};
};

12
arch/arm/boot/dts/st/stm32mp157c-ed1.dts
View File

@ -10,6 +10,7 @@
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
@ -71,6 +72,17 @@
};
};
led {
compatible = "gpio-leds";
led-blue {
gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
};
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";

19
arch/arm/boot/dts/st/stm32mp15xc.dtsi
View File

@ -4,15 +4,14 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/ {
soc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
&etzpc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc 9>;
status = "disabled";
};
};

82
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
View File

@ -6,6 +6,23 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
<STM32_PINMUX('B', 4, AF9)>; /* I2C2_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c2_sleep_pins_a: i2c2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* I2C2_SCL */
<STM32_PINMUX('B', 4, ANALOG)>; /* I2C2_SDA */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
@ -60,6 +77,28 @@
};
};
spi3_pins_a: spi3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 7, AF1)>, /* SPI3_SCK */
<STM32_PINMUX('B', 8, AF1)>; /* SPI3_MOSI */
drive-push-pull;
bias-disable;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 10, AF1)>; /* SPI3_MISO */
bias-disable;
};
};
spi3_sleep_pins_a: spi3-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 7, ANALOG)>, /* SPI3_SCK */
<STM32_PINMUX('B', 8, ANALOG)>, /* SPI3_MOSI */
<STM32_PINMUX('B', 10, ANALOG)>; /* SPI3_MISO */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
@ -90,3 +129,46 @@
};
};
};
&pinctrl_z {
i2c8_pins_a: i2c8-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C8_SCL */
<STM32_PINMUX('Z', 3, AF8)>; /* I2C8_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c8_sleep_pins_a: i2c8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C8_SCL */
<STM32_PINMUX('Z', 3, ANALOG)>; /* I2C8_SDA */
};
};
};
&pinctrl_z {
spi8_pins_a: spi8-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 2, AF3)>, /* SPI8_SCK */
<STM32_PINMUX('Z', 0, AF3)>; /* SPI8_MOSI */
drive-push-pull;
bias-disable;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */
bias-disable;
};
};
spi8_sleep_pins_a: spi8-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 2, ANALOG)>, /* SPI8_SCK */
<STM32_PINMUX('Z', 0, ANALOG)>, /* SPI8_MOSI */
<STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */
};
};
};

359
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@ -3,7 +3,9 @@
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
/ {
#address-cells = <2>;
@ -35,34 +37,16 @@
};
clocks {
ck_flexgen_08: ck-flexgen-08 {
clk_dsi_txbyte: txbyteclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-frequency = <0>;
};
ck_flexgen_51: ck-flexgen-51 {
clk_rcbsec: clk-rcbsec {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_ls_mcu: ck-icn-ls-mcu {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_p_vdec: ck-icn-p-vdec {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_p_venc: ck-icn-p-venc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-frequency = <64000000>;
};
};
@ -109,10 +93,10 @@
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
};
@ -123,18 +107,220 @@
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc-bus@42080000 {
compatible = "simple-bus";
rifsc: bus@42080000 {
compatible = "st,stm32mp25-rifsc", "simple-bus";
reg = <0x42080000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#access-controller-cells = <1>;
ranges;
spi2: spi@400b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x400b0000 0x400>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI2>;
resets = <&rcc SPI2_R>;
access-controllers = <&rifsc 23>;
status = "disabled";
};
spi3: spi@400c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x400c0000 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI3>;
resets = <&rcc SPI3_R>;
access-controllers = <&rifsc 24>;
status = "disabled";
};
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_08>;
clocks = <&rcc CK_KER_USART2>;
access-controllers = <&rifsc 32>;
status = "disabled";
};
i2c1: i2c@40120000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40120000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C1>;
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 41>;
status = "disabled";
};
i2c2: i2c@40130000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40130000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C2>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 42>;
status = "disabled";
};
i2c3: i2c@40140000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40140000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C3>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 43>;
status = "disabled";
};
i2c4: i2c@40150000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40150000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C4>;
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 44>;
status = "disabled";
};
i2c5: i2c@40160000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40160000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C5>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 45>;
status = "disabled";
};
i2c6: i2c@40170000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40170000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C6>;
resets = <&rcc I2C6_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 46>;
status = "disabled";
};
i2c7: i2c@40180000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40180000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C7>;
resets = <&rcc I2C7_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 47>;
status = "disabled";
};
spi1: spi@40230000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x40230000 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI1>;
resets = <&rcc SPI1_R>;
access-controllers = <&rifsc 22>;
status = "disabled";
};
spi4: spi@40240000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x40240000 0x400>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI4>;
resets = <&rcc SPI4_R>;
access-controllers = <&rifsc 25>;
status = "disabled";
};
spi5: spi@40280000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x40280000 0x400>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI5>;
resets = <&rcc SPI5_R>;
access-controllers = <&rifsc 26>;
status = "disabled";
};
spi6: spi@40350000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x40350000 0x400>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI6>;
resets = <&rcc SPI6_R>;
access-controllers = <&rifsc 27>;
status = "disabled";
};
spi7: spi@40360000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x40360000 0x400>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI7>;
resets = <&rcc SPI7_R>;
access-controllers = <&rifsc 28>;
status = "disabled";
};
spi8: spi@46020000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp25-spi";
reg = <0x46020000 0x400>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_SPI8>;
resets = <&rcc SPI8_R>;
access-controllers = <&rifsc 29>;
status = "disabled";
};
i2c8: i2c@46040000 {
compatible = "st,stm32mp25-i2c";
reg = <0x46040000 0x400>;
interrupt-names = "event";
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_I2C8>;
resets = <&rcc I2C8_R>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 48>;
status = "disabled";
};
@ -143,11 +329,13 @@
arm,primecell-periphid = <0x00353180>;
reg = <0x48220000 0x400>, <0x44230400 0x8>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_51>;
clocks = <&rcc CK_KER_SDMMC1 >;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
access-controllers = <&rifsc 76>;
status = "disabled";
};
};
@ -168,6 +356,93 @@
};
};
rcc: clock-controller@44200000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_ICN_VID>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_15>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_28>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_32>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_34>,
<&scmi_clk CK_SCMI_FLEXGEN_35>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_49>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_59>,
<&scmi_clk CK_SCMI_FLEXGEN_60>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
@ -186,7 +461,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
@ -197,7 +472,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
@ -208,7 +483,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
@ -219,7 +494,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
@ -230,7 +505,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
@ -241,7 +516,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
@ -252,7 +527,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
@ -263,7 +538,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
@ -274,7 +549,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
@ -285,7 +560,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
@ -296,7 +571,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
@ -315,7 +590,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&ck_icn_ls_mcu>;
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";

7
arch/arm64/boot/dts/st/stm32mp253.dtsi
View File

@ -20,4 +20,11 @@
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};

33
arch/arm64/boot/dts/st/stm32mp255.dtsi
View File

@ -5,22 +5,21 @@
*/
#include "stm32mp253.dtsi"
/ {
soc@0 {
rifsc: rifsc-bus@42080000 {
vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_icn_p_vdec>;
};
&rifsc {
vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_BUS_VDEC>;
access-controllers = <&rifsc 89>;
venc: venc@480e0000 {
compatible = "st,stm32mp25-venc";
reg = <0x480e0000 0x800>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_icn_ls_mcu>;
};
};
};
};
venc: venc@480e0000 {
compatible = "st,stm32mp25-venc";
reg = <0x480e0000 0x800>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_BUS_VENC>;
access-controllers = <&rifsc 90>;
};
};

34
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@ -55,6 +55,26 @@
status = "okay";
};
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
pinctrl-1 = <&i2c2_sleep_pins_a>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <13>;
clock-frequency = <400000>;
status = "okay";
};
&i2c8 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c8_pins_a>;
pinctrl-1 = <&i2c8_sleep_pins_a>;
i2c-scl-rising-time-ns = <57>;
i2c-scl-falling-time-ns = <7>;
clock-frequency = <400000>;
status = "disabled";
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@ -68,6 +88,20 @@
status = "okay";
};
&spi3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_pins_a>;
pinctrl-1 = <&spi3_sleep_pins_a>;
status = "disabled";
};
&spi8 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi8_pins_a>;
pinctrl-1 = <&spi8_sleep_pins_a>;
status = "disabled";
};
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;