From 3f9bb601a10dbe3a9b506d9856708a67308bb860 Mon Sep 17 00:00:00 2001 From: Zan Dobersek Date: Thu, 29 Feb 2024 08:49:11 +0100 Subject: [PATCH] drm/msm/a7xx: allow writing to CP_BV counter selection registers In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling purposes of tools like fdperf and perfetto. Signed-off-by: Zan Dobersek Patchwork: https://patchwork.freedesktop.org/patch/580548/ [fixup a730_protect size] Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index cf0b1de1c071..65a9663db3a5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1255,8 +1255,9 @@ static const u32 a730_protect[] = { A6XX_PROTECT_NORDWR(0x00699, 0x01e9), A6XX_PROTECT_NORDWR(0x008a0, 0x0008), A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */ - A6XX_PROTECT_RDONLY(0x008de, 0x0154), + /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ + A6XX_PROTECT_NORDWR(0x008de, 0x0001), + A6XX_PROTECT_RDONLY(0x008e7, 0x014b), A6XX_PROTECT_NORDWR(0x00900, 0x004d), A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), A6XX_PROTECT_NORDWR(0x00a41, 0x01be), @@ -1291,8 +1292,7 @@ static const u32 a730_protect[] = { A6XX_PROTECT_RDONLY(0x1f844, 0x007b), A6XX_PROTECT_NORDWR(0x1f860, 0x0000), A6XX_PROTECT_NORDWR(0x1f878, 0x002a), - /* CP_PROTECT_REG[44, 46] are left untouched! */ - 0, + /* CP_PROTECT_REG[45, 46] are left untouched! */ 0, 0, A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),