Merge branch 'for-5.5/clk' into for-5.5/memory
This commit is contained in:
Thierry Reding
commit
3feb4a3cf0
@ -17,7 +17,9 @@ obj-y += clk-tegra-fixed.o
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obj-y += clk-tegra-super-gen4.o
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obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20-emc.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
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293
drivers/clk/tegra/clk-tegra20-emc.c
Normal file
293
drivers/clk/tegra/clk-tegra20-emc.c
Normal file
@ -0,0 +1,293 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Based on drivers/clk/tegra/clk-emc.c
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Dmitry Osipenko <digetx@gmail.com>
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* Copyright (C) 2019 GRATE-DRIVER project
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*/
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#define pr_fmt(fmt) "tegra-emc-clk: " fmt
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/tegra.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK GENMASK(7, 0)
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#define CLK_SOURCE_EMC_2X_CLK_SRC_MASK GENMASK(31, 30)
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#define CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT 30
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#define MC_EMC_SAME_FREQ BIT(16)
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#define USE_PLLM_UD BIT(29)
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#define EMC_SRC_PLL_M 0
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#define EMC_SRC_PLL_C 1
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#define EMC_SRC_PLL_P 2
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#define EMC_SRC_CLK_M 3
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static const char * const emc_parent_clk_names[] = {
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"pll_m", "pll_c", "pll_p", "clk_m",
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};
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struct tegra_clk_emc {
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struct clk_hw hw;
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void __iomem *reg;
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bool mc_same_freq;
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bool want_low_jitter;
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tegra20_clk_emc_round_cb *round_cb;
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void *cb_arg;
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};
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static inline struct tegra_clk_emc *to_tegra_clk_emc(struct clk_hw *hw)
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{
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return container_of(hw, struct tegra_clk_emc, hw);
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}
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static unsigned long emc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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val = readl_relaxed(emc->reg);
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div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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return DIV_ROUND_UP(parent_rate * 2, div + 2);
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}
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static u8 emc_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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}
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static int emc_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
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val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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unsigned int index;
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u32 val, div;
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div = div_frac_get(rate, parent_rate, 8, 1, 0);
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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val |= div;
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index = val >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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div = div_frac_get(rate, parent_rate, 8, 1, 0);
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
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val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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val |= div;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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struct clk_hw *parent_hw;
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unsigned long divided_rate;
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unsigned long parent_rate;
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unsigned int i;
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long emc_rate;
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int div;
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emc_rate = emc->round_cb(req->rate, req->min_rate, req->max_rate,
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emc->cb_arg);
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if (emc_rate < 0)
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return emc_rate;
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for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
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parent_hw = clk_hw_get_parent_by_index(hw, i);
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if (req->best_parent_hw == parent_hw)
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parent_rate = req->best_parent_rate;
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else
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parent_rate = clk_hw_get_rate(parent_hw);
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if (emc_rate > parent_rate)
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continue;
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div = div_frac_get(emc_rate, parent_rate, 8, 1, 0);
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divided_rate = DIV_ROUND_UP(parent_rate * 2, div + 2);
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if (divided_rate != emc_rate)
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continue;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent_hw;
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req->rate = emc_rate;
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break;
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}
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if (i == ARRAY_SIZE(emc_parent_clk_names)) {
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pr_err_once("can't find parent for rate %lu emc_rate %lu\n",
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req->rate, emc_rate);
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return -EINVAL;
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}
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return 0;
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}
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static const struct clk_ops tegra_clk_emc_ops = {
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.recalc_rate = emc_recalc_rate,
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.get_parent = emc_get_parent,
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.set_parent = emc_set_parent,
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.set_rate = emc_set_rate,
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.set_rate_and_parent = emc_set_rate_and_parent,
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.determine_rate = emc_determine_rate,
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};
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void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
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void *cb_arg)
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{
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struct clk *clk = __clk_lookup("emc");
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struct tegra_clk_emc *emc;
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struct clk_hw *hw;
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if (clk) {
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hw = __clk_get_hw(clk);
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emc = to_tegra_clk_emc(hw);
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emc->round_cb = round_cb;
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emc->cb_arg = cb_arg;
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}
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}
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bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw)
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{
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return to_tegra_clk_emc(emc_hw)->round_cb != NULL;
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}
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struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter)
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{
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struct tegra_clk_emc *emc;
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struct clk_init_data init;
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struct clk *clk;
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emc = kzalloc(sizeof(*emc), GFP_KERNEL);
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if (!emc)
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return NULL;
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/*
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* EMC stands for External Memory Controller.
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*
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* We don't want EMC clock to be disabled ever by gating its
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* parent and whatnot because system is busted immediately in that
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* case, hence the clock is marked as critical.
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*/
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init.name = "emc";
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init.ops = &tegra_clk_emc_ops;
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init.flags = CLK_IS_CRITICAL;
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init.parent_names = emc_parent_clk_names;
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init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
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emc->reg = ioaddr;
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emc->hw.init = &init;
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emc->want_low_jitter = low_jitter;
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clk = clk_register(NULL, &emc->hw);
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if (IS_ERR(clk)) {
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kfree(emc);
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return NULL;
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}
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return clk;
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}
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int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
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{
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struct tegra_clk_emc *emc;
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struct clk_hw *hw;
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if (!emc_clk)
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return -EINVAL;
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hw = __clk_get_hw(emc_clk);
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emc = to_tegra_clk_emc(hw);
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emc->mc_same_freq = same;
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return 0;
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}
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@ -130,8 +130,6 @@ static struct cpu_clk_suspend_context {
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static void __iomem *clk_base;
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static void __iomem *pmc_base;
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static DEFINE_SPINLOCK(emc_lock);
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#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
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@ -760,7 +758,6 @@ static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
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static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
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static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
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"clk_m" };
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static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
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static struct tegra_periph_init_data tegra_periph_clk_list[] = {
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TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
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@ -787,41 +784,6 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
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TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
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};
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static void __init tegra20_emc_clk_init(void)
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{
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const u32 use_pllm_ud = BIT(29);
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struct clk *clk;
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u32 emc_reg;
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clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
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ARRAY_SIZE(mux_pllmcp_clkm),
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CLK_SET_RATE_NO_REPARENT,
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clk_base + CLK_SOURCE_EMC,
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30, 2, 0, &emc_lock);
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clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
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&emc_lock);
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clks[TEGRA20_CLK_MC] = clk;
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/* un-divided pll_m_out0 is currently unsupported */
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emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC);
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if (emc_reg & use_pllm_ud) {
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pr_err("%s: un-divided PllM_out0 used as clock source\n",
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__func__);
|
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return;
|
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}
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/*
|
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* Note that 'emc_mux' source and 'emc' rate shouldn't be changed at
|
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* the same time due to a HW bug, this won't happen because we're
|
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* defining 'emc_mux' and 'emc' as distinct clocks.
|
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*/
|
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clk = tegra_clk_register_divider("emc", "emc_mux",
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clk_base + CLK_SOURCE_EMC, CLK_IS_CRITICAL,
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TEGRA_DIVIDER_INT, 0, 8, 1, &emc_lock);
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clks[TEGRA20_CLK_EMC] = clk;
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}
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static void __init tegra20_periph_clk_init(void)
|
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{
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struct tegra_periph_init_data *data;
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@ -835,7 +797,13 @@ static void __init tegra20_periph_clk_init(void)
|
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clks[TEGRA20_CLK_AC97] = clk;
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/* emc */
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tegra20_emc_clk_init();
|
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clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
|
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|
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clks[TEGRA20_CLK_EMC] = clk;
|
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|
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clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
|
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NULL);
|
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clks[TEGRA20_CLK_MC] = clk;
|
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|
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/* dsi */
|
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clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
|
||||
@ -1115,6 +1083,8 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
|
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if (IS_ERR(clk))
|
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return clk;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
|
||||
/*
|
||||
* Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
|
||||
* clock is created by the pinctrl driver. It is possible for clk user
|
||||
@ -1124,13 +1094,16 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
|
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*/
|
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if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
|
||||
clkspec->args[0] == TEGRA20_CLK_CDEV2) {
|
||||
hw = __clk_get_hw(clk);
|
||||
|
||||
parent_hw = clk_hw_get_parent(hw);
|
||||
if (!parent_hw)
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
if (clkspec->args[0] == TEGRA20_CLK_EMC) {
|
||||
if (!tegra20_clk_emc_driver_available(hw))
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
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return clk;
|
||||
}
|
||||
|
||||
|
||||
@ -151,7 +151,6 @@ static unsigned long input_freq;
|
||||
|
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static DEFINE_SPINLOCK(cml_lock);
|
||||
static DEFINE_SPINLOCK(pll_d_lock);
|
||||
static DEFINE_SPINLOCK(emc_lock);
|
||||
|
||||
#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
|
||||
_clk_num, _gate_flags, _clk_id) \
|
||||
@ -808,7 +807,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
||||
[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
|
||||
[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
|
||||
[tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
|
||||
[tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true },
|
||||
[tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },
|
||||
};
|
||||
|
||||
static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
|
||||
@ -995,7 +994,6 @@ static void __init tegra30_super_clk_init(void)
|
||||
static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
|
||||
static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
|
||||
static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
|
||||
@ -1044,14 +1042,12 @@ static void __init tegra30_periph_clk_init(void)
|
||||
clks[TEGRA30_CLK_AFI] = clk;
|
||||
|
||||
/* emc */
|
||||
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
|
||||
ARRAY_SIZE(mux_pllmcp_clkm),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
clk_base + CLK_SOURCE_EMC,
|
||||
30, 2, 0, &emc_lock);
|
||||
clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
|
||||
|
||||
clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
|
||||
&emc_lock);
|
||||
clks[TEGRA30_CLK_EMC] = clk;
|
||||
|
||||
clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
|
||||
NULL);
|
||||
clks[TEGRA30_CLK_MC] = clk;
|
||||
|
||||
/* cml0 */
|
||||
@ -1302,6 +1298,26 @@ static struct tegra_audio_clk_info tegra30_audio_plls[] = {
|
||||
{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
|
||||
};
|
||||
|
||||
static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct clk *clk;
|
||||
|
||||
clk = of_clk_src_onecell_get(clkspec, data);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
|
||||
if (clkspec->args[0] == TEGRA30_CLK_EMC) {
|
||||
if (!tegra20_clk_emc_driver_available(hw))
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init tegra30_clock_init(struct device_node *np)
|
||||
{
|
||||
struct device_node *node;
|
||||
@ -1345,7 +1361,7 @@ static void __init tegra30_clock_init(struct device_node *np)
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
||||
tegra_add_of_provider(np, of_clk_src_onecell_get);
|
||||
tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
|
||||
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
|
||||
|
||||
tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
|
||||
|
||||
@ -838,4 +838,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
|
||||
udelay(delay); \
|
||||
} while (0)
|
||||
|
||||
bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw);
|
||||
struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
|
||||
|
||||
#endif /* TEGRA_CLK_H */
|
||||
|
||||
@ -119,4 +119,15 @@ extern void tegra210_put_utmipll_in_iddq(void);
|
||||
extern void tegra210_put_utmipll_out_iddq(void);
|
||||
extern int tegra210_clk_handle_mbist_war(unsigned int id);
|
||||
|
||||
struct clk;
|
||||
|
||||
typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
|
||||
unsigned long min_rate,
|
||||
unsigned long max_rate,
|
||||
void *arg);
|
||||
|
||||
void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
|
||||
void *cb_arg);
|
||||
int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
|
||||
|
||||
#endif /* __LINUX_CLK_TEGRA_H_ */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user