drm/vmwgfx: Rename stream output target binding tracker struct
Previous name vmw_ctx_bindinfo_so is misleading because it actually represent so target and stream output is a new resource type that needs tracking for SM5 capable device. Also rename binding type enum and internal functions to reflect these belongs to so targets. Signed-off-by: Deepak Rawat <drawat.floss@gmail.com> Reviewed-by: Thomas Hellström (VMware) <thomas_os@shipmail.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Roland Scheidegger <sroland@vmware.com>
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@ -57,7 +57,7 @@
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#define VMW_BINDING_RT_BIT 0
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#define VMW_BINDING_PS_BIT 1
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#define VMW_BINDING_SO_BIT 2
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#define VMW_BINDING_SO_T_BIT 2
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#define VMW_BINDING_VB_BIT 3
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#define VMW_BINDING_UAV_BIT 4
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#define VMW_BINDING_CS_UAV_BIT 5
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@ -98,7 +98,7 @@ struct vmw_ctx_binding_state {
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struct vmw_ctx_bindinfo_view render_targets[SVGA3D_RT_MAX];
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struct vmw_ctx_bindinfo_tex texture_units[SVGA3D_NUM_TEXTURE_UNITS];
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struct vmw_ctx_bindinfo_view ds_view;
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struct vmw_ctx_bindinfo_so so_targets[SVGA3D_DX_MAX_SOTARGETS];
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struct vmw_ctx_bindinfo_so_target so_targets[SVGA3D_DX_MAX_SOTARGETS];
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struct vmw_ctx_bindinfo_vb vertex_buffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
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struct vmw_ctx_bindinfo_ib index_buffer;
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struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE];
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@ -119,7 +119,7 @@ static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind);
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static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs);
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static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi,
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bool rebind);
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@ -187,7 +187,7 @@ static const size_t vmw_binding_sr_offsets[] = {
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offsetof(struct vmw_ctx_binding_state, per_shader[4].shader_res),
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offsetof(struct vmw_ctx_binding_state, per_shader[5].shader_res),
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};
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static const size_t vmw_binding_so_offsets[] = {
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static const size_t vmw_binding_so_target_offsets[] = {
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offsetof(struct vmw_ctx_binding_state, so_targets),
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};
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static const size_t vmw_binding_vb_offsets[] = {
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@ -236,10 +236,10 @@ static const struct vmw_binding_info vmw_binding_infos[] = {
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.size = sizeof(struct vmw_ctx_bindinfo_view),
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.offsets = vmw_binding_dx_ds_offsets,
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.scrub_func = vmw_binding_scrub_dx_rt},
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[vmw_ctx_binding_so] = {
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.size = sizeof(struct vmw_ctx_bindinfo_so),
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.offsets = vmw_binding_so_offsets,
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.scrub_func = vmw_binding_scrub_so},
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[vmw_ctx_binding_so_target] = {
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.size = sizeof(struct vmw_ctx_bindinfo_so_target),
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.offsets = vmw_binding_so_target_offsets,
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.scrub_func = vmw_binding_scrub_so_target},
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[vmw_ctx_binding_vb] = {
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.size = sizeof(struct vmw_ctx_bindinfo_vb),
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.offsets = vmw_binding_vb_offsets,
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@ -874,8 +874,8 @@ static void vmw_collect_so_targets(struct vmw_ctx_binding_state *cbs,
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const struct vmw_ctx_bindinfo *bi,
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u32 max_num)
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{
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const struct vmw_ctx_bindinfo_so *biso =
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container_of(bi, struct vmw_ctx_bindinfo_so, bi);
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const struct vmw_ctx_bindinfo_so_target *biso =
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container_of(bi, struct vmw_ctx_bindinfo_so_target, bi);
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unsigned long i;
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SVGA3dSoTarget *so_buffer = (SVGA3dSoTarget *) cbs->bind_cmd_buffer;
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@ -900,11 +900,11 @@ static void vmw_collect_so_targets(struct vmw_ctx_binding_state *cbs,
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}
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/**
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* vmw_binding_emit_set_so - Issue delayed streamout binding commands
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* vmw_emit_set_so_target - Issue delayed streamout binding commands
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*
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* @cbs: Pointer to the context's struct vmw_ctx_binding_state
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*/
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static int vmw_emit_set_so(struct vmw_ctx_binding_state *cbs)
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static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs)
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{
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const struct vmw_ctx_bindinfo *loc = &cbs->so_targets[0].bi;
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struct {
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@ -1136,8 +1136,8 @@ static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs)
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case VMW_BINDING_PS_BIT:
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ret = vmw_binding_emit_dirty_ps(cbs);
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break;
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case VMW_BINDING_SO_BIT:
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ret = vmw_emit_set_so(cbs);
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case VMW_BINDING_SO_T_BIT:
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ret = vmw_emit_set_so_target(cbs);
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break;
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case VMW_BINDING_VB_BIT:
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ret = vmw_emit_set_vb(cbs);
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@ -1201,18 +1201,18 @@ static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind)
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}
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/**
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* vmw_binding_scrub_so - Schedule a dx streamoutput buffer binding
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* vmw_binding_scrub_so_target - Schedule a dx streamoutput buffer binding
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* scrub from a context
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*
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* @bi: single binding information.
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* @rebind: Whether to issue a bind instead of scrub command.
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*/
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static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind)
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static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind)
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{
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struct vmw_ctx_binding_state *cbs =
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vmw_context_binding_state(bi->ctx);
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__set_bit(VMW_BINDING_SO_BIT, &cbs->dirty);
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__set_bit(VMW_BINDING_SO_T_BIT, &cbs->dirty);
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return 0;
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}
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@ -1387,7 +1387,7 @@ u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
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[vmw_ctx_binding_rt] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_dx_rt] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_ds] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_so] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_so_target] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_uav] = VMW_RES_DIRTY_SET,
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[vmw_ctx_binding_cs_uav] = VMW_RES_DIRTY_SET,
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};
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@ -50,7 +50,7 @@ enum vmw_ctx_binding_type {
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vmw_ctx_binding_dx_rt,
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vmw_ctx_binding_sr,
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vmw_ctx_binding_ds,
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vmw_ctx_binding_so,
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vmw_ctx_binding_so_target,
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vmw_ctx_binding_vb,
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vmw_ctx_binding_ib,
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vmw_ctx_binding_uav,
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@ -132,14 +132,14 @@ struct vmw_ctx_bindinfo_view {
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};
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/**
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* struct vmw_ctx_bindinfo_so - StreamOutput binding metadata
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* struct vmw_ctx_bindinfo_so_target - StreamOutput binding metadata
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*
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* @bi: struct vmw_ctx_bindinfo we derive from.
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* @offset: Device data used to reconstruct binding command.
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* @size: Device data used to reconstruct binding command.
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* @slot: Device data used to reconstruct binding command.
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*/
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struct vmw_ctx_bindinfo_so {
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struct vmw_ctx_bindinfo_so_target {
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struct vmw_ctx_bindinfo bi;
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uint32 offset;
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uint32 size;
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@ -2479,7 +2479,7 @@ static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv,
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SVGA3dCmdHeader *header)
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{
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struct vmw_ctx_validation_info *ctx_node = VMW_GET_CTX_NODE(sw_context);
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struct vmw_ctx_bindinfo_so binding;
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struct vmw_ctx_bindinfo_so_target binding;
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struct vmw_resource *res;
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struct {
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SVGA3dCmdHeader header;
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@ -2509,7 +2509,7 @@ static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv,
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binding.bi.ctx = ctx_node->ctx;
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binding.bi.res = res;
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binding.bi.bt = vmw_ctx_binding_so,
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binding.bi.bt = vmw_ctx_binding_so_target,
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binding.offset = cmd->targets[i].offset;
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binding.size = cmd->targets[i].sizeInBytes;
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binding.slot = i;
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