drm/amdgpu/gmc: use proper register for vram type on Fiji
commit b634de4f446c062a0c95ec4d150b4cf7c85e3526 upstream. The offset changed on Fiji. Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -862,6 +862,8 @@ static int gmc_v8_0_late_init(void *handle)
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return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
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}
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#define mmMC_SEQ_MISC0_FIJI 0xA71
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static int gmc_v8_0_sw_init(void *handle)
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{
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int r;
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@ -875,7 +877,12 @@ static int gmc_v8_0_sw_init(void *handle)
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if (adev->flags & AMD_IS_APU) {
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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} else {
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u32 tmp = RREG32(mmMC_SEQ_MISC0);
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u32 tmp;
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if (adev->asic_type == CHIP_FIJI)
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tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
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else
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tmp = RREG32(mmMC_SEQ_MISC0);
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tmp &= MC_SEQ_MISC0__MT__MASK;
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adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
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}
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