intel-gpio for v6.8-1
* Use RAII for locking in the Tangier family of drivers (Raag) * Update Tangier family of drivers to use new PM helpers (Raag) The following is an automated git shortlog grouped by driver: elkhartlake: - reuse pm_ops from Intel Tangier driver tangier: - simplify locking using cleanup helpers - unexport suspend/resume handles - use EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS() helper -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmWAKJYACgkQb7wzTHR8 rCjgSA//dMmLE4gqJazEtqZd0T0XWwEeJfDpESebxnHaBMbleryosEaS6TLF5sFY Dstwmcn1bt1OEB+i1ALjh6X2YuVbYXx8i+XxpQ6nVBh9UIxt6jaN7IsGLdx4Yzcd NFWX+DKYBUV7kCtFDVjFeLGobLHr3fLV8UgSKqg82rLAmDBHixmtkTqYNtfZXZQI 4wfthz2KD++jceV6jG/5TllPKgqNZDIg8TvZqtpopaNju/Fmk5bQLUfIA/LtOUly K3kQsXq1lro4S4TTMpAsKzboC1vfORTzOyB8bQxCCQ+UvEYDe6QbJHooU7PoIQGN 2+liVgWr9uWFZcXEgziBm2UqtIS4WOk/4Qfvz4Dodw3v8UtACA9ajItNYw6sgx8j GzbU/3gnIq1U1OHESH/+1puxg0HKAHtJ4rnnFtJBTnuy/pM+nemRYumFzg0okGNx cw6aGuu3v3IxIZGzkCUdAABjE49QzQ8LYwafEa5dyKmONIm5O6zWR7gmNDoWKN1n boLlUfm+agf1fXy+rgEPw/MBKacJnLVr2B3XIScD+ZXUCTicbQRPBndgGE+Cvxcz 1hVUcQh5It1w5H/9Gwt1xivMo+hpe1vHLipa5mWkKT9F87SIKQpT2Y05CvoKernO wL2jJnnc7z58fIOgy0EQFhm25Lc9cSPGvJnuQGULdPh57y/y6fo= =TW/S -----END PGP SIGNATURE----- Merge tag 'intel-gpio-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into gpio/for-next intel-gpio for v6.8-1 * Use RAII for locking in the Tangier family of drivers (Raag) * Update Tangier family of drivers to use new PM helpers (Raag) The following is an automated git shortlog grouped by driver: elkhartlake: - reuse pm_ops from Intel Tangier driver tangier: - simplify locking using cleanup helpers - unexport suspend/resume handles - use EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS() helper
This commit is contained in:
Bartosz Golaszewski
commit
40aa7e290b
@ -55,18 +55,6 @@ static int ehl_gpio_probe(struct platform_device *pdev)
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return 0;
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}
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static int ehl_gpio_suspend(struct device *dev)
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{
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return tng_gpio_suspend(dev);
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}
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static int ehl_gpio_resume(struct device *dev)
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{
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return tng_gpio_resume(dev);
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(ehl_gpio_pm_ops, ehl_gpio_suspend, ehl_gpio_resume);
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static const struct platform_device_id ehl_gpio_ids[] = {
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{ "gpio-elkhartlake" },
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{ }
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@ -76,7 +64,7 @@ MODULE_DEVICE_TABLE(platform, ehl_gpio_ids);
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static struct platform_driver ehl_gpio_driver = {
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.driver = {
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.name = "gpio-elkhartlake",
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.pm = pm_sleep_ptr(&ehl_gpio_pm_ops),
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.pm = pm_sleep_ptr(&tng_gpio_pm_ops),
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},
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.probe = ehl_gpio_probe,
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.id_table = ehl_gpio_ids,
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@ -10,6 +10,7 @@
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*/
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#include <linux/bitops.h>
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#include <linux/cleanup.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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@ -19,6 +20,7 @@
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#include <linux/math.h>
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#include <linux/module.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pm.h>
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#include <linux/spinlock.h>
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#include <linux/string_helpers.h>
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#include <linux/types.h>
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@ -91,37 +93,31 @@ static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)
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static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *reg;
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u8 shift;
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reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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writel(BIT(shift), reg);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gpdr;
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u32 value;
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u8 shift;
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gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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value = readl(gpdr);
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value &= ~BIT(shift);
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writel(value, gpdr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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@ -129,21 +125,18 @@ static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset
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int value)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gpdr;
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u8 shift;
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gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
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tng_gpio_set(chip, offset, value);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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value = readl(gpdr);
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value |= BIT(shift);
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writel(value, gpdr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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@ -164,14 +157,13 @@ static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned int debounce)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gfbr;
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u32 value;
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u8 shift;
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gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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value = readl(gfbr);
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if (debounce)
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@ -180,8 +172,6 @@ static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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value |= BIT(shift);
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writel(value, gfbr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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@ -207,27 +197,25 @@ static void tng_irq_ack(struct irq_data *d)
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{
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struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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unsigned long flags;
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void __iomem *gisr;
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u8 shift;
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gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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writel(BIT(shift), gisr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
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{
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unsigned long flags;
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void __iomem *gimr;
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u32 value;
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u8 shift;
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gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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value = readl(gimr);
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if (unmask)
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@ -235,8 +223,6 @@ static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
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else
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value &= ~BIT(shift);
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writel(value, gimr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void tng_irq_mask(struct irq_data *d)
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@ -267,10 +253,9 @@ static int tng_irq_set_type(struct irq_data *d, unsigned int type)
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void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
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void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
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u8 shift = gpio % 32;
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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value = readl(grer);
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if (type & IRQ_TYPE_EDGE_RISING)
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@ -311,8 +296,6 @@ static int tng_irq_set_type(struct irq_data *d, unsigned int type)
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irq_set_handler_locked(d, handle_edge_irq);
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}
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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@ -324,10 +307,11 @@ static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
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void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr);
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void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr);
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u8 shift = gpio % 32;
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&priv->lock, flags);
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dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
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guard(raw_spinlock_irqsave)(&priv->lock);
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/* Clear the existing wake status */
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writel(BIT(shift), gwsr);
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@ -339,9 +323,6 @@ static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
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value &= ~BIT(shift);
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writel(value, gwmr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
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return 0;
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}
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@ -477,14 +458,13 @@ int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)
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}
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EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER);
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int tng_gpio_suspend(struct device *dev)
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static int tng_gpio_suspend(struct device *dev)
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{
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struct tng_gpio *priv = dev_get_drvdata(dev);
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struct tng_gpio_context *ctx = priv->ctx;
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unsigned long flags;
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unsigned int base;
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
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/* GPLR is RO, values read will be restored using GPSR */
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@ -498,20 +478,16 @@ int tng_gpio_suspend(struct device *dev)
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ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
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}
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER);
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int tng_gpio_resume(struct device *dev)
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static int tng_gpio_resume(struct device *dev)
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{
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struct tng_gpio *priv = dev_get_drvdata(dev);
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struct tng_gpio_context *ctx = priv->ctx;
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unsigned long flags;
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unsigned int base;
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raw_spin_lock_irqsave(&priv->lock, flags);
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guard(raw_spinlock_irqsave)(&priv->lock);
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for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
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/* GPLR is RO, values read will be restored using GPSR */
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@ -525,11 +501,10 @@ int tng_gpio_resume(struct device *dev)
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writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
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}
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER);
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EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(tng_gpio_pm_ops, tng_gpio_suspend, tng_gpio_resume, GPIO_TANGIER);
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MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
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MODULE_AUTHOR("Pandith N <pandith.n@intel.com>");
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@ -13,6 +13,7 @@
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#define _GPIO_TANGIER_H_
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#include <linux/gpio/driver.h>
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#include <linux/pm.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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@ -111,7 +112,6 @@ struct tng_gpio {
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int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio);
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int tng_gpio_suspend(struct device *dev);
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int tng_gpio_resume(struct device *dev);
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extern const struct dev_pm_ops tng_gpio_pm_ops;
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#endif /* _GPIO_TANGIER_H_ */
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