PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask()
Rename variable from data to d to maintain consistency between driver functions, such as dw_msi_mask_irq() and dw_msi_unmask_irq(). No functional change is intended. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Jingoo Han <jingoohan1@gmail.com>
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@ -149,20 +149,20 @@ static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
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return -EINVAL;
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return -EINVAL;
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}
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}
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static void dw_pci_bottom_mask(struct irq_data *data)
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static void dw_pci_bottom_mask(struct irq_data *d)
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{
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(data);
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned int res, bit, ctrl;
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unsigned int res, bit, ctrl;
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unsigned long flags;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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raw_spin_lock_irqsave(&pp->lock, flags);
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if (pp->ops->msi_clear_irq) {
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if (pp->ops->msi_clear_irq) {
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pp->ops->msi_clear_irq(pp, data->hwirq);
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pp->ops->msi_clear_irq(pp, d->hwirq);
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} else {
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} else {
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ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_status[ctrl] &= ~(1 << bit);
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pp->irq_status[ctrl] &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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@ -172,20 +172,20 @@ static void dw_pci_bottom_mask(struct irq_data *data)
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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}
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static void dw_pci_bottom_unmask(struct irq_data *data)
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static void dw_pci_bottom_unmask(struct irq_data *d)
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{
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(data);
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned int res, bit, ctrl;
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unsigned int res, bit, ctrl;
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unsigned long flags;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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raw_spin_lock_irqsave(&pp->lock, flags);
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if (pp->ops->msi_set_irq) {
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if (pp->ops->msi_set_irq) {
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pp->ops->msi_set_irq(pp, data->hwirq);
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pp->ops->msi_set_irq(pp, d->hwirq);
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} else {
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} else {
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ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_status[ctrl] |= 1 << bit;
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pp->irq_status[ctrl] |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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