media: camss: csiphy: Add support for 8x96
Add CSIPHY hardware dependent part for 8x96. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Todor Tomov
Mauro Carvalho Chehab
parent
369f81f350
commit
4138a88b60
@ -4,6 +4,7 @@ qcom-camss-objs += \
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camss.o \
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camss-csid.o \
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camss-csiphy-2ph-1-0.o \
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camss-csiphy-3ph-1-0.o \
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camss-csiphy.o \
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camss-ispif.o \
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camss-vfe.o \
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256
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
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256
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
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@ -0,0 +1,256 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* camss-csiphy-3ph-1-0.c
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*
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* Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
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*
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* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2016-2018 Linaro Ltd.
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*/
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#include "camss-csiphy.h"
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6))
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#define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3)
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#define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
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#define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
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#define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50
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#define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa
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#define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2)
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#define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0)
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#define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2
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#define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0)
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#define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1)
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#define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1
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#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n))
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
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#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n))
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static void csiphy_hw_version_read(struct csiphy_device *csiphy,
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struct device *dev)
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{
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u32 hw_version;
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writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID,
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csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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hw_version = readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12));
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8;
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16;
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24;
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dev_err(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
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}
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/*
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* csiphy_reset - Perform software reset on CSIPHY module
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* @csiphy: CSIPHY device
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*/
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static void csiphy_reset(struct csiphy_device *csiphy)
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{
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writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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usleep_range(5000, 8000);
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writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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}
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static irqreturn_t csiphy_isr(int irq, void *dev)
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{
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struct csiphy_device *csiphy = dev;
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int i;
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for (i = 0; i < 11; i++) {
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int c = i + 22;
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u8 val = readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i));
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writel_relaxed(val, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c));
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}
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writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
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writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
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for (i = 22; i < 33; i++)
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writel_relaxed(0x0, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
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return IRQ_HANDLED;
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}
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/*
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* csiphy_settle_cnt_calc - Calculate settle count value
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*
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* Helper function to calculate settle count value. This is
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* based on the CSI2 T_hs_settle parameter which in turn
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* is calculated based on the CSI2 transmitter pixel clock
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* frequency.
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*
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* Return settle count value or 0 if the CSI2 pixel clock
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* frequency is not available
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*/
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static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes,
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u32 timer_clk_rate)
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{
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u32 mipi_clock; /* Hz */
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u32 ui; /* ps */
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u32 timer_period; /* ps */
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u32 t_hs_prepare_max; /* ps */
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u32 t_hs_settle; /* ps */
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u8 settle_cnt;
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mipi_clock = pixel_clock * bpp / (2 * num_lanes);
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ui = div_u64(1000000000000LL, mipi_clock);
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ui /= 2;
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t_hs_prepare_max = 85000 + 6 * ui;
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t_hs_settle = t_hs_prepare_max;
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timer_period = div_u64(1000000000000LL, timer_clk_rate);
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settle_cnt = t_hs_settle / timer_period - 6;
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return settle_cnt;
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}
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static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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u32 pixel_clock, u8 bpp, u8 lane_mask)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val, l = 0;
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int i;
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settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data,
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csiphy->timer_clk_rate);
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val = BIT(c->clk.pos);
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for (i = 0; i < c->num_data; i++)
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val |= BIT(c->data[i].pos * 2);
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
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val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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for (i = 0; i <= c->num_data; i++) {
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if (i == c->num_data)
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l = 7;
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else
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l = c->data[i].pos * 2;
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val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
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val |= 0x17;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
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val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
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val = settle_cnt;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
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val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM |
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CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
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val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
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val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
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val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP |
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CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
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val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
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val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
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val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL;
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writel_relaxed(val, csiphy->base +
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CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l));
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}
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val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
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val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
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val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12));
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val = 0xfb;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14));
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val = 0x7f;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17));
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val = 0xef;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21));
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}
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static void csiphy_lanes_disable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg)
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{
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writel_relaxed(0, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
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writel_relaxed(0, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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}
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const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
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.hw_version_read = csiphy_hw_version_read,
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.reset = csiphy_reset,
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.lanes_enable = csiphy_lanes_enable,
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.lanes_disable = csiphy_lanes_disable,
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.isr = csiphy_isr,
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};
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@ -565,6 +565,8 @@ int msm_csiphy_subdev_init(struct camss *camss,
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if (camss->version == CAMSS_8x16)
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csiphy->ops = &csiphy_ops_2ph_1_0;
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else if (camss->version == CAMSS_8x96)
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csiphy->ops = &csiphy_ops_3ph_1_0;
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else
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return -EINVAL;
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@ -85,5 +85,6 @@ int msm_csiphy_register_entity(struct csiphy_device *csiphy,
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void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
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extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
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extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
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#endif /* QC_MSM_CAMSS_CSIPHY_H */
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