dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for LPASS core clocks and audio clock IDs for LPASS client to request for the clocks. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220223172248.18877-1-tdas@codeaurora.org
This commit is contained in:
Taniya Das
Bjorn Andersson
parent
3123109284
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm LPASS core and audio clock control module which supports the
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clocks and power domains on SC7280.
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See also:
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- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
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- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
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properties:
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clocks: true
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clock-names: true
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compatible:
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enum:
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- qcom,sc7280-lpassaoncc
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- qcom,sc7280-lpassaudiocc
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- qcom,sc7280-lpasscorecc
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- qcom,sc7280-lpasshm
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power-domains:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: qcom,sc7280-lpassaudiocc
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then:
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properties:
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clocks:
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items:
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- description: Board XO source
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- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
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clock-names:
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items:
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- const: bi_tcxo
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- const: lpass_aon_cc_main_rcg_clk_src
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-lpassaoncc
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then:
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properties:
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clocks:
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items:
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- description: Board XO source
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- description: Board XO active only source
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- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: iface
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-lpasshm
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- qcom,sc7280-lpasscorecc
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then:
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properties:
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clocks:
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items:
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- description: Board XO source
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clock-names:
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items:
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- const: bi_tcxo
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpass_audiocc: clock-controller@3300000 {
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compatible = "qcom,sc7280-lpassaudiocc";
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reg = <0x3300000 0x30000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
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clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
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power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpass_hm: clock-controller@3c00000 {
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compatible = "qcom,sc7280-lpasshm";
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reg = <0x3c00000 0x28>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpasscore: clock-controller@3900000 {
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compatible = "qcom,sc7280-lpasscorecc";
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reg = <0x3900000 0x50000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpass_aon: clock-controller@3380000 {
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compatible = "qcom,sc7280-lpassaoncc";
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reg = <0x3380000 0x30000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
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<&lpasscore LPASS_CORE_CC_CORE_CLK>;
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clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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43
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
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43
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
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/* LPASS_AUDIO_CC clocks */
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#define LPASS_AUDIO_CC_PLL 0
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#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
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#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
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#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
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#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
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#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
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#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
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#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
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#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
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#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
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#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
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#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
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#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
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#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
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#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
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#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
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/* LPASS_AON_CC clocks */
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#define LPASS_AON_CC_PLL 0
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#define LPASS_AON_CC_PLL_OUT_EVEN 1
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#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
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#define LPASS_AON_CC_PLL_OUT_ODD 3
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#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
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#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
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#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
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#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
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#define LPASS_AON_CC_TX_MCLK_CLK 8
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#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
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#define LPASS_AON_CC_VA_MEM0_CLK 10
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/* LPASS_AON_CC power domains */
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#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
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#endif
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26
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
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26
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
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/* LPASS_CORE_CC clocks */
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#define LPASS_CORE_CC_DIG_PLL 0
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#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1
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#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2
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#define LPASS_CORE_CC_CORE_CLK 3
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#define LPASS_CORE_CC_CORE_CLK_SRC 4
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#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5
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#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6
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#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7
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#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8
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#define LPASS_CORE_CC_LPM_CORE_CLK 9
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#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
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#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
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/* LPASS_CORE_CC power domains */
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#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0
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#endif
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