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ASoC: SOF: Intel: mtl: Access MTL_HFPWRCTL from HDA_DSP_BAR

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The Host Power Management/Clock Control (ULP) Registers in
the HDA BAR shadow the values of the same registers in the DSP BAR,
so let's modify the latter - as done already for other accesses.

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230307095251.3058-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Yong Zhi 2023-03-07 11:52:51 +02:00 committed by Mark Brown
parent 1d045d7775
commit 418d2b2fad
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GPG Key ID: 24D68B725D5487D0
1 changed files with 1 additions and 1 deletions
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2
sound/soc/sof/intel/mtl.c
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@ -256,7 +256,7 @@ static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
dev_err(sdev->dev, "failed to power up gated DSP domain\n");
/* make sure SoundWire is not power-gated */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL,
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
return ret;
}