usb: dwc2: Rename hibernation to partial_power_down
No-op change, only rename. This code was misnamed originally. It was only responsible for partial power down and not for hibernation. Rename core_params->hibernation to core_params->power_down, dwc2_set_param_hibernation() to dwc2_set_param_power_down(). Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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7455f8b7f0
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41ba9b9b95
@ -128,17 +128,17 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
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}
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/**
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* dwc2_exit_hibernation() - Exit controller from Partial Power Down.
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* dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @restore: Controller registers need to be restored
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*/
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int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->params.hibernation)
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if (!hsotg->params.power_down)
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return -ENOTSUPP;
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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@ -182,16 +182,16 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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}
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/**
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* dwc2_enter_hibernation() - Put controller in Partial Power Down.
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* dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->params.hibernation)
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if (!hsotg->params.power_down)
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return -ENOTSUPP;
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/* Backup all registers */
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@ -220,7 +220,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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/*
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* Clear any pending interrupts since dwc2 will not be able to
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* clear them after entering hibernation.
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* clear them after entering partial_power_down.
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*/
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dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
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@ -421,9 +421,9 @@ enum dwc2_ep0_state {
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* case.
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* 0 - No (default)
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* 1 - Yes
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* @hibernation: Specifies whether the controller support hibernation.
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* If hibernation is enabled, the controller will enter
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* hibernation in both peripheral and host mode when
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* @power_down: Specifies whether the controller support power_down.
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* If power_down is enabled, the controller will enter
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* power_down in both peripheral and host mode when
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* needed.
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* 0 - No (default)
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* 1 - Yes
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@ -498,7 +498,7 @@ struct dwc2_core_params {
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bool reload_ctl;
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bool uframe_sched;
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bool external_id_pin_ctl;
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bool hibernation;
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bool power_down;
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bool lpm;
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bool lpm_clock_gating;
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bool besl;
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@ -1117,8 +1117,8 @@ static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
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*/
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int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
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int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
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int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
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int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
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int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
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bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
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void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
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@ -321,10 +321,10 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
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if (dwc2_is_device_mode(hsotg)) {
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if (hsotg->lx_state == DWC2_L2) {
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ret = dwc2_exit_hibernation(hsotg, true);
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ret = dwc2_exit_partial_power_down(hsotg, true);
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if (ret && (ret != -ENOTSUPP))
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dev_err(hsotg->dev,
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"exit hibernation failed\n");
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"exit power_down failed\n");
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}
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/*
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@ -417,16 +417,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
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/* Clear Remote Wakeup Signaling */
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dctl &= ~DCTL_RMTWKUPSIG;
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dwc2_writel(dctl, hsotg->regs + DCTL);
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ret = dwc2_exit_hibernation(hsotg, true);
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ret = dwc2_exit_partial_power_down(hsotg, true);
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if (ret && (ret != -ENOTSUPP))
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dev_err(hsotg->dev, "exit hibernation failed\n");
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dev_err(hsotg->dev, "exit power_down failed\n");
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call_gadget(hsotg, resume);
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}
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/* Change to L0 state */
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hsotg->lx_state = DWC2_L0;
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} else {
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if (hsotg->params.hibernation)
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if (hsotg->params.power_down)
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return;
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if (hsotg->lx_state != DWC2_L1) {
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@ -497,11 +497,11 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
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return;
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}
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ret = dwc2_enter_hibernation(hsotg);
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ret = dwc2_enter_partial_power_down(hsotg);
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if (ret) {
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if (ret != -ENOTSUPP)
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dev_err(hsotg->dev,
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"enter hibernation failed\n");
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"enter power_down failed\n");
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goto skip_power_saving;
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}
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@ -718,7 +718,7 @@ static int params_show(struct seq_file *seq, void *v)
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print_param_hex(seq, p, ahbcfg);
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print_param(seq, p, uframe_sched);
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print_param(seq, p, external_id_pin_ctl);
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print_param(seq, p, hibernation);
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print_param(seq, p, power_down);
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print_param(seq, p, lpm);
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print_param(seq, p, lpm_clock_gating);
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print_param(seq, p, besl);
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@ -3527,7 +3527,7 @@ irq_retry:
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/* This event must be used only if controller is suspended */
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if (hsotg->lx_state == DWC2_L2) {
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dwc2_exit_hibernation(hsotg, true);
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dwc2_exit_partial_power_down(hsotg, true);
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hsotg->lx_state = DWC2_L0;
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}
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}
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@ -4374,11 +4374,11 @@ static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
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spin_lock_irqsave(&hsotg->lock, flags);
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/*
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* If controller is hibernated, it must exit from hibernation
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* If controller is hibernated, it must exit from power_down
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* before being initialized / de-initialized
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*/
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if (hsotg->lx_state == DWC2_L2)
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dwc2_exit_hibernation(hsotg, false);
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dwc2_exit_partial_power_down(hsotg, false);
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if (is_active) {
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hsotg->op_state = OTG_STATE_B_PERIPHERAL;
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@ -3397,10 +3397,10 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
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hsotg->bus_suspended = true;
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/*
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* If hibernation is supported, Phy clock will be suspended
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* If power_down is supported, Phy clock will be suspended
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* after registers are backuped.
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*/
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if (!hsotg->params.hibernation) {
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if (!hsotg->params.power_down) {
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/* Suspend the Phy Clock */
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pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgctl |= PCGCTL_STOPPCLK;
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@ -3432,10 +3432,10 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
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spin_lock_irqsave(&hsotg->lock, flags);
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/*
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* If hibernation is supported, Phy clock is already resumed
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* If power_down is supported, Phy clock is already resumed
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* after registers restore.
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*/
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if (!hsotg->params.hibernation) {
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if (!hsotg->params.power_down) {
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pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgctl &= ~PCGCTL_STOPPCLK;
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dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
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@ -4364,7 +4364,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
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if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
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goto unlock;
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if (!hsotg->params.hibernation)
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if (!hsotg->params.power_down)
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goto skip_power_saving;
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/*
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@ -4378,12 +4378,12 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
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dwc2_writel(hprt0, hsotg->regs + HPRT0);
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}
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/* Enter hibernation */
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ret = dwc2_enter_hibernation(hsotg);
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/* Enter partial_power_down */
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ret = dwc2_enter_partial_power_down(hsotg);
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if (ret) {
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if (ret != -ENOTSUPP)
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dev_err(hsotg->dev,
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"enter hibernation failed\n");
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"enter partial_power_down failed\n");
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goto skip_power_saving;
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}
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@ -4394,7 +4394,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
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spin_lock_irqsave(&hsotg->lock, flags);
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}
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/* After entering hibernation, hardware is no more accessible */
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/* After entering partial_power_down, hardware is no more accessible */
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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skip_power_saving:
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@ -4419,7 +4419,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
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if (hsotg->lx_state != DWC2_L2)
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goto unlock;
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if (!hsotg->params.hibernation) {
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if (!hsotg->params.power_down) {
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hsotg->lx_state = DWC2_L0;
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goto unlock;
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}
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@ -4441,10 +4441,10 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
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spin_lock_irqsave(&hsotg->lock, flags);
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}
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/* Exit hibernation */
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ret = dwc2_exit_hibernation(hsotg, true);
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/* Exit partial_power_down */
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ret = dwc2_exit_partial_power_down(hsotg, true);
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if (ret && (ret != -ENOTSUPP))
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dev_err(hsotg->dev, "exit hibernation failed\n");
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dev_err(hsotg->dev, "exit partial_power_down failed\n");
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hsotg->lx_state = DWC2_L0;
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@ -278,7 +278,7 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
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p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
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p->uframe_sched = true;
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p->external_id_pin_ctl = false;
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p->hibernation = false;
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p->power_down = false;
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p->lpm = true;
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p->lpm_clock_gating = true;
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p->besl = true;
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