mfd: rtsx: Add support for rts525A
Add support for new chip rts525A. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Micky Ching
Lee Jones
parent
663c425f2c
commit
41bc233473
@ -487,3 +487,106 @@ void rts524a_init_params(struct rtsx_pcr *pcr)
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pcr->ops = &rts524a_pcr_ops;
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}
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static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
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LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
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return rtsx_base_card_power_on(pcr, card);
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}
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static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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switch (voltage) {
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case OUTPUT_3V3:
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rtsx_pci_write_register(pcr, LDO_CONFIG2,
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LDO_D3318_MASK, LDO_D3318_33V);
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rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
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break;
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case OUTPUT_1V8:
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rtsx_pci_write_register(pcr, LDO_CONFIG2,
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LDO_D3318_MASK, LDO_D3318_18V);
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rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
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SD_IO_USING_1V8);
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break;
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default:
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return -EINVAL;
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}
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rtsx_pci_init_cmd(pcr);
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rts5249_fill_driving(pcr, voltage);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
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D3_DELINK_MODE_EN, 0x00);
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if (err < 0)
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return err;
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rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
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_PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
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_PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
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_PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
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rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
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_PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
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_PHY_CMU_DEBUG_EN);
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if (is_version(pcr, 0x525A, IC_VER_A))
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rtsx_pci_write_phy_register(pcr, _PHY_REV0,
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_PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
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_PHY_REV0_CDR_RX_IDLE_BYPASS);
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return 0;
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}
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static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rts5249_extra_init_hw(pcr);
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rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
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if (is_version(pcr, 0x525A, IC_VER_A)) {
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rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
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L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
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rtsx_pci_write_register(pcr, RREF_CFG,
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RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
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rtsx_pci_write_register(pcr, LDO_VIO_CFG,
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LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
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rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
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LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
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rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
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LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
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rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
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LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
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rtsx_pci_write_register(pcr, OOBS_CONFIG,
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OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
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}
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return 0;
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}
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static const struct pcr_ops rts525a_pcr_ops = {
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.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
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.extra_init_hw = rts525a_extra_init_hw,
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.optimize_phy = rts525a_optimize_phy,
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.turn_on_led = rtsx_base_turn_on_led,
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.turn_off_led = rtsx_base_turn_off_led,
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.enable_auto_blink = rtsx_base_enable_auto_blink,
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.disable_auto_blink = rtsx_base_disable_auto_blink,
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.card_power_on = rts525a_card_power_on,
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.card_power_off = rtsx_base_card_power_off,
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.switch_output_voltage = rts525a_switch_output_voltage,
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.force_power_down = rtsx_base_force_power_down,
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};
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void rts525a_init_params(struct rtsx_pcr *pcr)
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{
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rts5249_init_params(pcr);
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pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
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pcr->ops = &rts525a_pcr_ops;
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}
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@ -59,6 +59,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
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{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ 0, }
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};
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@ -1114,6 +1115,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
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rts524a_init_params(pcr);
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break;
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case 0x525A:
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rts525a_init_params(pcr);
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break;
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case 0x5287:
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rtl8411b_init_params(pcr);
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break;
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@ -1159,7 +1164,7 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
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struct rtsx_pcr *pcr;
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struct pcr_handle *handle;
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u32 base, len;
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int ret, i;
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int ret, i, bar = 0;
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dev_dbg(&(pcidev->dev),
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": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
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@ -1204,8 +1209,10 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
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pcr->pci = pcidev;
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dev_set_drvdata(&pcidev->dev, handle);
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len = pci_resource_len(pcidev, 0);
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base = pci_resource_start(pcidev, 0);
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if (CHK_PCI_PID(pcr, 0x525A))
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bar = 1;
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len = pci_resource_len(pcidev, bar);
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base = pci_resource_start(pcidev, bar);
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pcr->remap_addr = ioremap_nocache(base, len);
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if (!pcr->remap_addr) {
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ret = -ENOMEM;
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@ -40,6 +40,7 @@ void rtl8402_init_params(struct rtsx_pcr *pcr);
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void rts5227_init_params(struct rtsx_pcr *pcr);
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void rts5249_init_params(struct rtsx_pcr *pcr);
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void rts524a_init_params(struct rtsx_pcr *pcr);
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void rts525a_init_params(struct rtsx_pcr *pcr);
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void rtl8411b_init_params(struct rtsx_pcr *pcr);
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static inline u8 map_sd_drive(int idx)
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@ -727,6 +727,10 @@
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#define PHY_SSCCR3 0x03
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#define PHY_SSCCR3_STEP_IN 0x2740
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#define PHY_SSCCR3_CHECK_DELAY 0x0008
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#define _PHY_ANA03 0x03
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#define _PHY_ANA03_TIMER_MAX 0x2700
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#define _PHY_ANA03_OOBS_DEB_EN 0x0040
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#define _PHY_CMU_DEBUG_EN 0x0008
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#define PHY_RTCR 0x04
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#define PHY_RDR 0x05
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@ -785,6 +789,10 @@
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#define PHY_REV_STOP_CLKRD 0x0020
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#define PHY_REV_RX_PWST 0x0008
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#define PHY_REV_STOP_CLKWR 0x0004
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#define _PHY_REV0 0x19
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#define _PHY_REV0_FILTER_OUT 0x3800
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#define _PHY_REV0_CDR_BYPASS_PFD 0x0100
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#define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
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#define PHY_FLD0 0x1A
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#define PHY_ANA1A 0x1A
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@ -800,6 +808,13 @@
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#define PHY_FLD3_RXDELINK 0x0004
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#define PHY_ANA1D 0x1D
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#define PHY_ANA1D_DEBUG_ADDR 0x0004
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#define _PHY_FLD0 0x1D
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#define _PHY_FLD0_CLK_REQ_20C 0x8000
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#define _PHY_FLD0_RX_IDLE_EN 0x1000
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#define _PHY_FLD0_BIT_ERR_RSTN 0x0800
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#define _PHY_FLD0_BER_COUNT 0x01E0
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#define _PHY_FLD0_BER_TIMER 0x001E
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#define _PHY_FLD0_CHECK_EN 0x0001
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#define PHY_FLD4 0x1E
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#define PHY_FLD4_FLDEN_SEL 0x4000
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