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MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.

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Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2009-05-12 12:41:53 -07:00 committed by Ralf Baechle
parent 95affdda9b
commit 41f0e4d041
2 changed files with 6 additions and 1 deletions
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4
arch/mips/include/asm/cpu-features.h
View File

@ -147,6 +147,10 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2) cpu_has_mips64r1 | cpu_has_mips64r2)
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
#endif
/* /*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels

3
arch/mips/mm/tlbex.c
View File

@ -259,7 +259,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
} }
if (cpu_has_mips_r2) { if (cpu_has_mips_r2) {
uasm_i_ehb(p); if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(p);
tlbw(p); tlbw(p);
return; return;
} }