crypto: hisilicon/hpre - support last word dumping
1. Add some debugging registers. 2. Add last word dumping function during hpre engine controller reset. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Kai Ye
Herbert Xu
parent
8a88d09145
commit
42123e81fd
@ -36,6 +36,12 @@
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#define HPRE_DATA_WUSER_CFG 0x301040
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#define HPRE_INT_MASK 0x301400
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#define HPRE_INT_STATUS 0x301800
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#define HPRE_HAC_INT_MSK 0x301400
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#define HPRE_HAC_RAS_CE_ENB 0x301410
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#define HPRE_HAC_RAS_NFE_ENB 0x301414
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#define HPRE_HAC_RAS_FE_ENB 0x301418
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#define HPRE_HAC_INT_SET 0x301500
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#define HPRE_RNG_TIMEOUT_NUM 0x301A34
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#define HPRE_CORE_INT_ENABLE 0
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#define HPRE_CORE_INT_DISABLE GENMASK(21, 0)
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#define HPRE_RDCHN_INI_ST 0x301a00
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@ -201,28 +207,32 @@ static const u64 hpre_cluster_offsets[] = {
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};
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static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = {
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{"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET},
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{"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET},
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{"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET},
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{"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET},
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{"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET},
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{"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET},
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{"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET},
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{"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET},
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{"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET},
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{"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET},
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};
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static const struct debugfs_reg32 hpre_com_dfx_regs[] = {
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{"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE},
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{"AXQOS ", HPRE_VFG_AXQOS},
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{"AWUSR_CFG ", HPRE_AWUSR_FP_CFG},
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{"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1},
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{"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1},
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{"BD_ENDIAN ", HPRE_BD_ENDIAN},
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{"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS},
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{"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG},
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{"POISON_BYPASS ", HPRE_POISON_BYPASS},
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{"BD_ARUSER ", HPRE_BD_ARUSR_CFG},
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{"BD_AWUSER ", HPRE_BD_AWUSR_CFG},
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{"DATA_ARUSER ", HPRE_DATA_RUSER_CFG},
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{"DATA_AWUSER ", HPRE_DATA_WUSER_CFG},
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{"INT_STATUS ", HPRE_INT_STATUS},
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{"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE},
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{"AXQOS ", HPRE_VFG_AXQOS},
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{"AWUSR_CFG ", HPRE_AWUSR_FP_CFG},
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{"BD_ENDIAN ", HPRE_BD_ENDIAN},
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{"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS},
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{"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG},
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{"POISON_BYPASS ", HPRE_POISON_BYPASS},
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{"BD_ARUSER ", HPRE_BD_ARUSR_CFG},
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{"BD_AWUSER ", HPRE_BD_AWUSR_CFG},
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{"DATA_ARUSER ", HPRE_DATA_RUSER_CFG},
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{"DATA_AWUSER ", HPRE_DATA_WUSER_CFG},
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{"INT_STATUS ", HPRE_INT_STATUS},
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{"INT_MASK ", HPRE_HAC_INT_MSK},
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{"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB},
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{"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB},
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{"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB},
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{"INT_SET ", HPRE_HAC_INT_SET},
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{"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM},
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};
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static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = {
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@ -1023,6 +1033,82 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
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return hisi_qm_init(qm);
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}
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static int hpre_show_last_regs_init(struct hisi_qm *qm)
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{
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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u8 clusters_num = hpre_cluster_num(qm);
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struct qm_debug *debug = &qm->debug;
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void __iomem *io_base;
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int i, j, idx;
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debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
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com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
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if (!debug->last_words)
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return -ENOMEM;
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for (i = 0; i < com_dfx_regs_num; i++)
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debug->last_words[i] = readl_relaxed(qm->io_base +
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hpre_com_dfx_regs[i].offset);
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for (i = 0; i < clusters_num; i++) {
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io_base = qm->io_base + hpre_cluster_offsets[i];
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for (j = 0; j < cluster_dfx_regs_num; j++) {
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idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
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debug->last_words[idx] = readl_relaxed(
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io_base + hpre_cluster_dfx_regs[j].offset);
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}
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}
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return 0;
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}
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static void hpre_show_last_regs_uninit(struct hisi_qm *qm)
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{
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struct qm_debug *debug = &qm->debug;
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if (qm->fun_type == QM_HW_VF || !debug->last_words)
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return;
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kfree(debug->last_words);
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debug->last_words = NULL;
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}
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static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
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{
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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u8 clusters_num = hpre_cluster_num(qm);
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struct qm_debug *debug = &qm->debug;
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struct pci_dev *pdev = qm->pdev;
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void __iomem *io_base;
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int i, j, idx;
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u32 val;
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if (qm->fun_type == QM_HW_VF || !debug->last_words)
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return;
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/* dumps last word of the debugging registers during controller reset */
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for (i = 0; i < com_dfx_regs_num; i++) {
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val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);
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if (debug->last_words[i] != val)
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pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n",
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hpre_com_dfx_regs[i].name, debug->last_words[i], val);
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}
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for (i = 0; i < clusters_num; i++) {
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io_base = qm->io_base + hpre_cluster_offsets[i];
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for (j = 0; j < cluster_dfx_regs_num; j++) {
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val = readl_relaxed(io_base +
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hpre_cluster_dfx_regs[j].offset);
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idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
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if (debug->last_words[idx] != val)
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pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n",
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i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val);
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}
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}
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}
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static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)
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{
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const struct hpre_hw_error *err = hpre_hw_errors;
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@ -1081,6 +1167,7 @@ static const struct hisi_qm_err_ini hpre_err_ini = {
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.open_axi_master_ooo = hpre_open_axi_master_ooo,
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.open_sva_prefetch = hpre_open_sva_prefetch,
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.close_sva_prefetch = hpre_close_sva_prefetch,
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.show_last_dfx_regs = hpre_show_last_dfx_regs,
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.err_info_init = hpre_err_info_init,
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};
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@ -1098,8 +1185,11 @@ static int hpre_pf_probe_init(struct hpre *hpre)
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qm->err_ini = &hpre_err_ini;
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qm->err_ini->err_info_init(qm);
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hisi_qm_dev_err_init(qm);
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ret = hpre_show_last_regs_init(qm);
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if (ret)
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pci_err(qm->pdev, "Failed to init last word regs!\n");
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return 0;
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return ret;
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}
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static int hpre_probe_init(struct hpre *hpre)
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@ -1185,6 +1275,7 @@ err_with_qm_start:
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hisi_qm_stop(qm, QM_NORMAL);
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err_with_err_init:
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hpre_show_last_regs_uninit(qm);
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hisi_qm_dev_err_uninit(qm);
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err_with_qm_init:
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@ -1215,6 +1306,7 @@ static void hpre_remove(struct pci_dev *pdev)
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if (qm->fun_type == QM_HW_PF) {
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hpre_cnt_regs_clear(qm);
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qm->debug.curr_qm_qp_num = 0;
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hpre_show_last_regs_uninit(qm);
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hisi_qm_dev_err_uninit(qm);
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}
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