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Merge 3.8-rc5 into driver-core-next

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This resolves a gpio driver merge issue pointed out in linux-next.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2013-01-25 21:06:30 -08:00
commit 422d26b6ec
248 changed files with 2066 additions and 1234 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
View File

@ -81,7 +81,8 @@ PA31 TXD4
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin need a pull up.
@ -126,7 +127,7 @@ pinctrl@fffff400 {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph with pullup */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};

18
Documentation/filesystems/f2fs.txt
View File

@ -175,9 +175,9 @@ consists of multiple segments as described below.
align with the zone size <-|
|-> align with the segment size
_________________________________________________________________________
| | | Node | Segment | Segment | |
| Superblock | Checkpoint | Address | Info. | Summary | Main |
| (SB) | (CP) | Table (NAT) | Table (SIT) | Area (SSA) | |
| | | Segment | Node | Segment | |
| Superblock | Checkpoint | Info. | Address | Summary | Main |
| (SB) | (CP) | Table (SIT) | Table (NAT) | Area (SSA) | |
|____________|_____2______|______N______|______N______|______N_____|__N___|
. .
. .
@ -200,14 +200,14 @@ consists of multiple segments as described below.
: It contains file system information, bitmaps for valid NAT/SIT sets, orphan
inode lists, and summary entries of current active segments.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Information Table (SIT)
: It contains segment information such as valid block count and bitmap for the
validity of all the blocks.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Summary Area (SSA)
: It contains summary entries which contains the owner information of all the
data and node blocks stored in Main area.
@ -236,13 +236,13 @@ For file system consistency, each CP points to which NAT and SIT copies are
valid, as shown as below.
+--------+----------+---------+
| CP | NAT | SIT |
| CP | SIT | NAT |
+--------+----------+---------+
. . . .
. . . .
. . . .
+-------+-------+--------+--------+--------+--------+
| CP #0 | CP #1 | NAT #0 | NAT #1 | SIT #0 | SIT #1 |
| CP #0 | CP #1 | SIT #0 | SIT #1 | NAT #0 | NAT #1 |
+-------+-------+--------+--------+--------+--------+
| ^ ^
| | |

2
MAINTAINERS
View File

@ -6585,7 +6585,7 @@ F: drivers/media/platform/s3c-camif/
F: include/media/s3c_camif.h
SERIAL DRIVERS
M: Alan Cox <alan@linux.intel.com>
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial

4
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 8
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME = Terrified Chipmunk
# *DOCUMENTATION*
@ -169,7 +169,7 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
-e s/arm.*/arm/ -e s/sa110/arm/ \
-e s/s390x/s390/ -e s/parisc64/parisc/ \
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
-e s/sh[234].*/sh/ )
-e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ )
# Cross compiling and selecting different set of gcc/bin-utils
# ---------------------------------------------------------------------------

2
arch/arm/boot/dts/armada-370-db.dts
View File

@ -26,7 +26,7 @@
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {

14
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -50,27 +50,25 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>;
interrupts = <87>, <88>, <89>;
};
};
};

21
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -51,39 +51,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {

21
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -66,39 +66,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {

4
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -336,8 +336,8 @@
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
gpios = <&pioA 25 0 /* sda */
&pioA 26 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;

60
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -143,6 +143,11 @@
atmel,pins =
<0 3 0x1 0x0>; /* PA3 periph A */
};
pinctrl_usart0_sck: usart0_sck-0 {
atmel,pins =
<0 4 0x1 0x0>; /* PA4 periph A */
};
};
usart1 {
@ -154,12 +159,17 @@
pinctrl_usart1_rts: usart1_rts-0 {
atmel,pins =
<3 27 0x3 0x0>; /* PC27 periph C */
<2 27 0x3 0x0>; /* PC27 periph C */
};
pinctrl_usart1_cts: usart1_cts-0 {
atmel,pins =
<3 28 0x3 0x0>; /* PC28 periph C */
<2 28 0x3 0x0>; /* PC28 periph C */
};
pinctrl_usart1_sck: usart1_sck-0 {
atmel,pins =
<2 28 0x3 0x0>; /* PC29 periph C */
};
};
@ -172,46 +182,56 @@
pinctrl_uart2_rts: uart2_rts-0 {
atmel,pins =
<0 0 0x2 0x0>; /* PB0 periph B */
<1 0 0x2 0x0>; /* PB0 periph B */
};
pinctrl_uart2_cts: uart2_cts-0 {
atmel,pins =
<0 1 0x2 0x0>; /* PB1 periph B */
<1 1 0x2 0x0>; /* PB1 periph B */
};
pinctrl_usart2_sck: usart2_sck-0 {
atmel,pins =
<1 2 0x2 0x0>; /* PB2 periph B */
};
};
usart3 {
pinctrl_uart3: usart3-0 {
atmel,pins =
<3 23 0x2 0x1 /* PC22 periph B with pullup */
3 23 0x2 0x0>; /* PC23 periph B */
<2 23 0x2 0x1 /* PC22 periph B with pullup */
2 23 0x2 0x0>; /* PC23 periph B */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<3 24 0x2 0x0>; /* PC24 periph B */
<2 24 0x2 0x0>; /* PC24 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<3 25 0x2 0x0>; /* PC25 periph B */
<2 25 0x2 0x0>; /* PC25 periph B */
};
pinctrl_usart3_sck: usart3_sck-0 {
atmel,pins =
<2 26 0x2 0x0>; /* PC26 periph B */
};
};
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<3 8 0x3 0x0 /* PC8 periph C */
3 9 0x3 0x1>; /* PC9 periph C with pullup */
<2 8 0x3 0x0 /* PC8 periph C */
2 9 0x3 0x1>; /* PC9 periph C with pullup */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<3 16 0x3 0x0 /* PC16 periph C */
3 17 0x3 0x1>; /* PC17 periph C with pullup */
<2 16 0x3 0x0 /* PC16 periph C */
2 17 0x3 0x1>; /* PC17 periph C with pullup */
};
};
@ -240,14 +260,14 @@
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
atmel,pins =
<1 8 0x1 0x0 /* PA8 periph A */
1 11 0x1 0x0 /* PA11 periph A */
1 12 0x1 0x0 /* PA12 periph A */
1 13 0x1 0x0 /* PA13 periph A */
1 14 0x1 0x0 /* PA14 periph A */
1 15 0x1 0x0 /* PA15 periph A */
1 16 0x1 0x0 /* PA16 periph A */
1 17 0x1 0x0>; /* PA17 periph A */
<1 8 0x1 0x0 /* PB8 periph A */
1 11 0x1 0x0 /* PB11 periph A */
1 12 0x1 0x0 /* PB12 periph A */
1 13 0x1 0x0 /* PB13 periph A */
1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x0 /* PB15 periph A */
1 16 0x1 0x0 /* PB16 periph A */
1 17 0x1 0x0>; /* PB17 periph A */
};
};

12
arch/arm/boot/dts/cros5250-common.dtsi
View File

@ -96,8 +96,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -120,8 +120,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -141,8 +141,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;

14
arch/arm/boot/dts/dove-cubox.dts
View File

@ -26,10 +26,15 @@
};
&uart0 { status = "okay"; };
&sdio0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
&sdio0 {
status = "okay";
/* sdio0 card detect is connected to wrong pin on CuBox */
cd-gpios = <&gpio0 12 1>;
};
&spi0 {
status = "okay";
@ -42,9 +47,14 @@
};
&pinctrl {
pinctrl-0 = <&pmx_gpio_18>;
pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>;
pinctrl-names = "default";
pmx_gpio_12: pmx-gpio-12 {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
pmx_gpio_18: pmx-gpio-18 {
marvell,pins = "mpp18";
marvell,function = "gpio";

8
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -115,8 +115,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -139,8 +139,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;

16
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
View File

@ -1,4 +1,5 @@
/include/ "kirkwood.dtsi"
/include/ "kirkwood-6281.dtsi"
/ {
chosen {
@ -6,6 +7,21 @@
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
&pmx_ns2_sata0 &pmx_ns2_sata1>;
pinctrl-names = "default";
pmx_ns2_sata0: pmx-ns2-sata0 {
marvell,pins = "mpp21";
marvell,function = "sata0";
};
pmx_ns2_sata1: pmx-ns2-sata1 {
marvell,pins = "mpp20";
marvell,function = "sata1";
};
};
serial@12000 {
clock-frequency = <166666667>;
status = "okay";

2
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -36,6 +36,7 @@
reg = <0x10100 0x40>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <35>, <36>, <37>, <38>;
};
@ -46,6 +47,7 @@
reg = <0x10140 0x40>;
ngpios = <18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <39>, <40>, <41>;
};

2
arch/arm/boot/dts/kizbox.dts
View File

@ -48,6 +48,8 @@
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};

6
arch/arm/boot/dts/sunxi.dtsi
View File

@ -60,19 +60,21 @@
};
uart0: uart@01c28000 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};
uart1: uart@01c28400 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};

2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -45,7 +45,6 @@
reg = <1>;
};
/* A7s disabled till big.LITTLE patches are available...
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -63,7 +62,6 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
};
*/
};
memory@80000000 {

3
arch/arm/configs/at91_dt_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

2
arch/arm/kernel/debug.S
View File

@ -100,12 +100,14 @@ ENTRY(printch)
b 1b
ENDPROC(printch)
#ifdef CONFIG_MMU
ENTRY(debug_ll_addr)
addruart r2, r3, ip
str r2, [r0]
str r3, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
#else

5
arch/arm/kernel/head.S
View File

@ -246,6 +246,7 @@ __create_page_tables:
/*
* Then map boot params address in r2 if specified.
* We map 2 sections in case the ATAGs/DTB crosses a section boundary.
*/
mov r0, r2, lsr #SECTION_SHIFT
movs r0, r0, lsl #SECTION_SHIFT
@ -253,6 +254,8 @@ __create_page_tables:
addne r3, r3, #PAGE_OFFSET
addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
orrne r6, r7, r0
strne r6, [r3], #1 << PMD_ORDER
addne r6, r6, #1 << SECTION_SHIFT
strne r6, [r3]
#ifdef CONFIG_DEBUG_LL
@ -331,7 +334,7 @@ ENTRY(secondary_startup)
* as it has already been validated by the primary processor.
*/
#ifdef CONFIG_ARM_VIRT_EXT
bl __hyp_stub_install
bl __hyp_stub_install_secondary
#endif
safe_svcmode_maskall r9

18
arch/arm/kernel/hyp-stub.S
View File

@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary)
* immediately.
*/
compare_cpu_mode_with_primary r4, r5, r6, r7
bxne lr
movne pc, lr
/*
* Once we have given up on one CPU, we do not try to install the
@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary)
*/
cmp r4, #HYP_MODE
bxne lr @ give up if the CPU is not in HYP mode
movne pc, lr @ give up if the CPU is not in HYP mode
/*
* Configure HSCTLR to set correct exception endianness/instruction set
@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary)
* Eventually, CPU-specific code might be needed -- assume not for now
*
* This code relies on the "eret" instruction to synchronize the
* various coprocessor accesses.
* various coprocessor accesses. This is done when we switch to SVC
* (see safe_svcmode_maskall).
*/
@ Now install the hypervisor stub:
adr r7, __hyp_stub_vectors
@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
1:
#endif
bic r7, r4, #MODE_MASK
orr r7, r7, #SVC_MODE
THUMB( orr r7, r7, #PSR_T_BIT )
msr spsr_cxsf, r7 @ This is SPSR_hyp.
__MSR_ELR_HYP(14) @ msr elr_hyp, lr
__ERET @ return, switching to SVC mode
@ The boot CPU mode is left in r4.
bx lr @ The boot CPU mode is left in r4.
ENDPROC(__hyp_stub_install_secondary)
__hyp_stub_do_trap:
@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors)
@ fall through
ENTRY(__hyp_set_vectors)
__HVC(0)
bx lr
mov pc, lr
ENDPROC(__hyp_set_vectors)
#ifndef ZIMAGE

2
arch/arm/mach-at91/setup.c
View File

@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base)
switch (socid) {
case ARCH_ID_AT91RM9200:
at91_soc_initdata.type = AT91_SOC_RM9200;
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
at91_boot_soc = at91rm9200_soc;
break;

1
arch/arm/mach-imx/Kconfig
View File

@ -851,6 +851,7 @@ config SOC_IMX6Q
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select HAVE_SMP
select MFD_SYSCON
select PINCTRL

6
arch/arm/mach-imx/clk-imx25.c
View File

@ -254,9 +254,9 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
/* i.mx25 has the i.mx35 type cspi */
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");

6
arch/arm/mach-imx/clk-imx27.c
View File

@ -236,9 +236,9 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");

6
arch/arm/mach-imx/clk-imx31.c
View File

@ -139,9 +139,9 @@ int __init mx31_clocks_init(unsigned long fref)
clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
/* i.mx31 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");

6
arch/arm/mach-imx/clk-imx35.c
View File

@ -251,9 +251,9 @@ int __init mx35_clocks_init()
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");

6
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -269,9 +269,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");

3
arch/arm/mach-imx/clk-imx6q.c
View File

@ -436,6 +436,9 @@ int __init mx6q_clocks_init(void)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);

1
arch/arm/mach-imx/common.h
View File

@ -142,6 +142,7 @@ extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_clock_map_io(void);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_PM
extern void imx6q_pm_init(void);

1
arch/arm/mach-imx/devices/devices-common.h
View File

@ -63,6 +63,7 @@ struct platform_device *__init imx_add_flexcan(
#include <linux/fsl_devices.h>
struct imx_fsl_usb2_udc_data {
const char *devid;
resource_size_t iobase;
resource_size_t irq;
};

15
arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
View File

@ -11,35 +11,36 @@
#include "../hardware.h"
#include "devices-common.h"
#define imx_fsl_usb2_udc_data_entry_single(soc) \
#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \
{ \
.devid = _devid, \
.iobase = soc ## _USB_OTG_BASE_ADDR, \
.irq = soc ## _INT_USB_OTG, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX25);
imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX27);
imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX31);
imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX35);
imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX51
const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX51);
imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
#endif
struct platform_device *__init imx_add_fsl_usb2_udc(
@ -57,7 +58,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
return imx_add_platform_device_dmamask(data->devid, -1,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}

2
arch/arm/mach-imx/devices/platform-imx-fb.c
View File

@ -54,7 +54,7 @@ struct platform_device *__init imx_add_imx_fb(
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("imx-fb", 0,
return imx_add_platform_device_dmamask(data->devid, 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}

12
arch/arm/mach-imx/hotplug.c
View File

@ -46,9 +46,11 @@ static inline void cpu_enter_lowpower(void)
void imx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
imx_enable_cpu(cpu, false);
/* spin here until hardware takes it down */
while (1)
;
cpu_do_idle();
}
int imx_cpu_kill(unsigned int cpu)
{
imx_enable_cpu(cpu, false);
return 1;
}

3
arch/arm/mach-imx/iram_alloc.c
View File

@ -22,8 +22,7 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/genalloc.h>
#include "iram.h"
#include "linux/platform_data/imx-iram.h"
static unsigned long iram_phys_base;
static void __iomem *iram_virt_base;

1
arch/arm/mach-imx/platsmp.c
View File

@ -92,5 +92,6 @@ struct smp_operations imx_smp_ops __initdata = {
.smp_boot_secondary = imx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = imx_cpu_die,
.cpu_kill = imx_cpu_kill,
#endif
};

1
arch/arm/mach-imx/pm-imx6q.c
View File

@ -41,6 +41,7 @@ static int imx6q_pm_enter(suspend_state_t state)
cpu_suspend(0, imx6q_suspend_finish);
imx_smp_prepare();
imx_gpc_post_resume();
imx6q_set_lpm(WAIT_CLOCKED);
break;
default:
return -EINVAL;

14
arch/arm/mach-integrator/pci_v3.c
View File

@ -475,13 +475,12 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
if (!ap_syscon_base)
return -EINVAL;
if (nr == 0) {
sys->mem_offset = PHYS_PCI_MEM_BASE;
ret = pci_v3_setup_resources(sys);
/* Remap the Integrator system controller */
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
if (!ap_syscon_base)
return -EINVAL;
}
return ret;
@ -497,6 +496,13 @@ void __init pci_v3_preinit(void)
unsigned int temp;
int ret;
/* Remap the Integrator system controller */
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
if (!ap_syscon_base) {
pr_err("unable to remap the AP syscon for PCIv3\n");
return;
}
pcibios_min_mem = 0x00100000;
/*

38
arch/arm/mach-kirkwood/board-ns2.c
View File

@ -18,47 +18,11 @@
#include <linux/gpio.h>
#include <linux/of.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data ns2_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
static unsigned int ns2_mpp_config[] __initdata = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Fan speed (bit 1) */
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Red led */
MPP14_GPIO, /* USB fuse */
MPP16_GPIO, /* SATA 0 power */
MPP17_GPIO, /* SATA 1 power */
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_SATA1_ACTn,
MPP21_SATA0_ACTn,
MPP22_GPIO, /* Fan speed (bit 0) */
MPP23_GPIO, /* Fan power */
MPP24_GPIO, /* USB mode select */
MPP25_GPIO, /* Fan rotation fail */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* Blue led (slow register) */
MPP30_GPIO, /* Blue led (command register) */
MPP31_GPIO, /* Board power off */
MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
MPP33_GPO, /* Fan speed (bit 2) */
0
};
#define NS2_GPIO_POWER_OFF 31
static void ns2_power_off(void)
@ -71,8 +35,6 @@ void __init ns2_init(void)
/*
* Basic setup. Needs to be called early.
*/
kirkwood_mpp_conf(ns2_mpp_config);
if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
of_machine_is_compatible("lacie,netspace_mini_v2"))
ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);

2
arch/arm/mach-mvebu/Makefile
View File

@ -1,6 +1,8 @@
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-orion/include
AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
obj-y += system-controller.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

6
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -397,6 +397,12 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP_PULL_ENA),
OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* UART2 - BT/FM/GPS shared transport */
OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};

2
arch/arm/mach-omap2/cclock2420_data.c
View File

@ -1935,6 +1935,8 @@ int __init omap2420_clk_init(void)
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap2xxx_clkt_vps_late_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,

2
arch/arm/mach-omap2/cclock2430_data.c
View File

@ -2050,6 +2050,8 @@ int __init omap2430_clk_init(void)
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap2xxx_clkt_vps_late_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,

13
arch/arm/mach-omap2/cclock44xx_data.c
View File

@ -2026,14 +2026,13 @@ int __init omap4xxx_clk_init(void)
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
if (cpu_is_omap446x()) {
rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
if (!rc)
rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
}
rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
if (!rc)
rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
return 0;
}

2
arch/arm/mach-omap2/devices.c
View File

@ -639,7 +639,7 @@ static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
return cnt;
}
static void omap_init_ocp2scp(void)
static void __init omap_init_ocp2scp(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;

3
arch/arm/mach-omap2/drm.c
View File

@ -25,6 +25,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_data/omap_drm.h>
#include "soc.h"
#include "omap_device.h"
#include "omap_hwmod.h"
@ -56,7 +57,7 @@ static int __init omap_init_drm(void)
oh->name);
}
platform_data.omaprev = GET_OMAP_REVISION();
platform_data.omaprev = GET_OMAP_TYPE;
return platform_device_register(&omap_drm_device);

6
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -2132,8 +2132,12 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
* currently reset very early during boot, before I2C is
* available, so it doesn't seem that we have any choice in
* the kernel other than to avoid resetting it.
*
* Also, McPDM needs to be configured to NO_IDLE mode when it
* is in used otherwise vital clocks will be gated which
* results 'slow motion' audio playback.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK,
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
.mpu_irqs = omap44xx_mcpdm_irqs,
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
.main_clk = "mcpdm_fck",

8
arch/arm/mach-omap2/timer.c
View File

@ -165,15 +165,11 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
struct device_node *np;
for_each_matching_node(np, match) {
if (!of_device_is_available(np)) {
of_node_put(np);
if (!of_device_is_available(np))
continue;
}
if (property && !of_get_property(np, property, NULL)) {
of_node_put(np);
if (property && !of_get_property(np, property, NULL))
continue;
}
of_add_property(np, &device_disabled);
return np;

2
arch/arm/mach-s3c64xx/mach-crag6410-module.c
View File

@ -47,7 +47,7 @@ static struct spi_board_info wm1253_devs[] = {
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.irq = S3C_EINT(5),
.irq = S3C_EINT(4),
.controller_data = &wm0010_spi_csinfo,
.platform_data = &wm0010_pdata,
},

2
arch/arm/mach-s3c64xx/pm.c
View File

@ -338,8 +338,10 @@ int __init s3c64xx_pm_init(void)
for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
#ifdef CONFIG_S3C_DEV_FB
if (dev_get_platdata(&s3c_device_fb.dev))
pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
#endif
return 0;
}

18
arch/arm/mm/dma-mapping.c
View File

@ -774,25 +774,27 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
size_t size, enum dma_data_direction dir,
void (*op)(const void *, size_t, int))
{
unsigned long pfn;
size_t left = size;
pfn = page_to_pfn(page) + offset / PAGE_SIZE;
offset %= PAGE_SIZE;
/*
* A single sg entry may refer to multiple physically contiguous
* pages. But we still need to process highmem pages individually.
* If highmem is not configured then the bulk of this loop gets
* optimized out.
*/
size_t left = size;
do {
size_t len = left;
void *vaddr;
page = pfn_to_page(pfn);
if (PageHighMem(page)) {
if (len + offset > PAGE_SIZE) {
if (offset >= PAGE_SIZE) {
page += offset / PAGE_SIZE;
offset %= PAGE_SIZE;
}
if (len + offset > PAGE_SIZE)
len = PAGE_SIZE - offset;
}
vaddr = kmap_high_get(page);
if (vaddr) {
vaddr += offset;
@ -809,7 +811,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
op(vaddr, len, dir);
}
offset = 0;
page++;
pfn++;
left -= len;
} while (left);
}

2
arch/arm/mm/mmu.c
View File

@ -283,7 +283,7 @@ static struct mem_type mem_types[] = {
},
[MT_MEMORY_SO] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_MT_UNCACHED,
L_PTE_MT_UNCACHED | L_PTE_XN,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
PMD_SECT_UNCACHED | PMD_SECT_XN,

2
arch/arm/plat-versatile/headsmp.S
View File

@ -20,7 +20,7 @@
*/
ENTRY(versatile_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
bic r0, #0xff000000
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5

6
arch/arm/vfp/entry.S
View File

@ -22,7 +22,7 @@
@ IRQs disabled.
@
ENTRY(do_vfp)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
add r11, r4, #1 @ increment it
str r11, [r10, #TI_PREEMPT]
@ -35,7 +35,7 @@ ENTRY(do_vfp)
ENDPROC(do_vfp)
ENTRY(vfp_null_entry)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it
@ -53,7 +53,7 @@ ENDPROC(vfp_null_entry)
__INIT
ENTRY(vfp_testing_entry)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it

4
arch/arm/vfp/vfphw.S
View File

@ -168,7 +168,7 @@ vfp_hw_state_valid:
@ else it's one 32-bit instruction, so
@ always subtract 4 from the following
@ instruction address.
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it
@ -192,7 +192,7 @@ look_for_VFP_exceptions:
@ not recognised by VFP
DBGSTR "not VFP"
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it

5
arch/arm64/include/asm/elf.h
View File

@ -26,7 +26,10 @@
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
#define ELF_CORE_COPY_REGS(dest, regs) \
*(struct user_pt_regs *)&(dest) = (regs)->user_regs;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fpsimd_state elf_fpregset_t;

27
arch/ia64/kernel/ptrace.c
View File

@ -672,33 +672,6 @@ ptrace_attach_sync_user_rbs (struct task_struct *child)
read_unlock(&tasklist_lock);
}
static inline int
thread_matches (struct task_struct *thread, unsigned long addr)
{
unsigned long thread_rbs_end;
struct pt_regs *thread_regs;
if (ptrace_check_attach(thread, 0) < 0)
/*
* If the thread is not in an attachable state, we'll
* ignore it. The net effect is that if ADDR happens
* to overlap with the portion of the thread's
* register backing store that is currently residing
* on the thread's kernel stack, then ptrace() may end
* up accessing a stale value. But if the thread
* isn't stopped, that's a problem anyhow, so we're
* doing as well as we can...
*/
return 0;
thread_regs = task_pt_regs(thread);
thread_rbs_end = ia64_get_user_rbs_end(thread, thread_regs, NULL);
if (!on_kernel_rbs(addr, thread_regs->ar_bspstore, thread_rbs_end))
return 0;
return 1; /* looks like we've got a winner */
}
/*
* Write f32-f127 back to task->thread.fph if it has been modified.
*/

16
arch/m68k/include/asm/dma-mapping.h
View File

@ -21,6 +21,22 @@ extern void *dma_alloc_coherent(struct device *, size_t,
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
static inline void *dma_alloc_attrs(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
return dma_alloc_coherent(dev, size, dma_handle, flag);
}
static inline void dma_free_attrs(struct device *dev, size_t size,
void *cpu_addr, dma_addr_t dma_handle,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
dma_free_coherent(dev, size, cpu_addr, dma_handle);
}
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{

2
arch/m68k/include/asm/pgtable_no.h
View File

@ -64,6 +64,8 @@ extern unsigned int kobjsize(const void *objp);
*/
#define VMALLOC_START 0
#define VMALLOC_END 0xffffffff
#define KMAP_START 0
#define KMAP_END 0xffffffff
#include <asm-generic/pgtable.h>

2
arch/m68k/include/asm/unistd.h
View File

@ -4,7 +4,7 @@
#include <uapi/asm/unistd.h>
#define NR_syscalls 348
#define NR_syscalls 349
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_OLD_STAT

1
arch/m68k/include/uapi/asm/unistd.h
View File

@ -353,5 +353,6 @@
#define __NR_process_vm_readv 345
#define __NR_process_vm_writev 346
#define __NR_kcmp 347
#define __NR_finit_module 348
#endif /* _UAPI_ASM_M68K_UNISTD_H_ */

1
arch/m68k/kernel/syscalltable.S
View File

@ -368,4 +368,5 @@ ENTRY(sys_call_table)
.long sys_process_vm_readv /* 345 */
.long sys_process_vm_writev
.long sys_kcmp
.long sys_finit_module

8
arch/m68k/mm/init.c
View File

@ -39,6 +39,11 @@
void *empty_zero_page;
EXPORT_SYMBOL(empty_zero_page);
#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
extern void init_pointer_table(unsigned long ptable);
extern pmd_t *zero_pgtable;
#endif
#ifdef CONFIG_MMU
pg_data_t pg_data_map[MAX_NUMNODES];
@ -69,9 +74,6 @@ void __init m68k_setup_node(int node)
node_set_online(node);
}
extern void init_pointer_table(unsigned long ptable);
extern pmd_t *zero_pgtable;
#else /* CONFIG_MMU */
/*

20
arch/parisc/kernel/entry.S
View File

@ -1865,7 +1865,7 @@ syscall_restore:
/* Are we being ptraced? */
ldw TASK_FLAGS(%r1),%r19
ldi (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
ldi _TIF_SYSCALL_TRACE_MASK,%r2
and,COND(=) %r19,%r2,%r0
b,n syscall_restore_rfi
@ -1978,15 +1978,23 @@ syscall_restore_rfi:
/* sr2 should be set to zero for userspace syscalls */
STREG %r0,TASK_PT_SR2(%r1)
pt_regs_ok:
LDREG TASK_PT_GR31(%r1),%r2
depi 3,31,2,%r2 /* ensure return to user mode. */
STREG %r2,TASK_PT_IAOQ0(%r1)
depi 3,31,2,%r2 /* ensure return to user mode. */
STREG %r2,TASK_PT_IAOQ0(%r1)
ldo 4(%r2),%r2
STREG %r2,TASK_PT_IAOQ1(%r1)
copy %r25,%r16
b intr_restore
nop
copy %r25,%r16
pt_regs_ok:
LDREG TASK_PT_IAOQ0(%r1),%r2
depi 3,31,2,%r2 /* ensure return to user mode. */
STREG %r2,TASK_PT_IAOQ0(%r1)
LDREG TASK_PT_IAOQ1(%r1),%r2
depi 3,31,2,%r2
STREG %r2,TASK_PT_IAOQ1(%r1)
b intr_restore
copy %r25,%r16
.import schedule,code
syscall_do_resched:

6
arch/parisc/kernel/irq.c
View File

@ -410,11 +410,13 @@ void __init init_IRQ(void)
{
local_irq_disable(); /* PARANOID - should already be disabled */
mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
claim_cpu_irqs();
#ifdef CONFIG_SMP
if (!cpu_eiem)
if (!cpu_eiem) {
claim_cpu_irqs();
cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
}
#else
claim_cpu_irqs();
cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
set_eiem(cpu_eiem); /* EIEM : enable all external intr */

2
arch/parisc/kernel/ptrace.c
View File

@ -26,7 +26,7 @@
#include <asm/asm-offsets.h>
/* PSW bits we allow the debugger to modify */
#define USER_PSW_BITS (PSW_N | PSW_V | PSW_CB)
#define USER_PSW_BITS (PSW_N | PSW_B | PSW_V | PSW_CB)
/*
* Called by kernel/ptrace.c when detaching..

4
arch/parisc/kernel/signal.c
View File

@ -190,8 +190,10 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
DBG(1,"get_sigframe: ka = %#lx, sp = %#lx, frame_size = %#lx\n",
(unsigned long)ka, sp, frame_size);
/* Align alternate stack and reserve 64 bytes for the signal
handler's frame marker. */
if ((ka->sa.sa_flags & SA_ONSTACK) != 0 && ! sas_ss_flags(sp))
sp = current->sas_ss_sp; /* Stacks grow up! */
sp = (current->sas_ss_sp + 0x7f) & ~0x3f; /* Stacks grow up! */
DBG(1,"get_sigframe: Returning sp = %#lx\n", (unsigned long)sp);
return (void __user *) sp; /* Stacks grow up. Fun. */

11
arch/parisc/math-emu/cnv_float.h
View File

@ -347,16 +347,15 @@
Sgl_isinexact_to_fix(sgl_value,exponent)
#define Duint_from_sgl_mantissa(sgl_value,exponent,dresultA,dresultB) \
{Sall(sgl_value) <<= SGL_EXP_LENGTH; /* left-justify */ \
{unsigned int val = Sall(sgl_value) << SGL_EXP_LENGTH; \
if (exponent <= 31) { \
Dintp1(dresultA) = 0; \
Dintp2(dresultB) = (unsigned)Sall(sgl_value) >> (31 - exponent); \
Dintp1(dresultA) = 0; \
Dintp2(dresultB) = val >> (31 - exponent); \
} \
else { \
Dintp1(dresultA) = Sall(sgl_value) >> (63 - exponent); \
Dintp2(dresultB) = Sall(sgl_value) << (exponent - 31); \
Dintp1(dresultA) = val >> (63 - exponent); \
Dintp2(dresultB) = exponent <= 62 ? val << (exponent - 31) : 0; \
} \
Sall(sgl_value) >>= SGL_EXP_LENGTH; /* return to original */ \
}
#define Duint_setzero(dresultA,dresultB) \

2
arch/powerpc/kvm/emulate.c
View File

@ -39,6 +39,7 @@
#define OP_31_XOP_TRAP 4
#define OP_31_XOP_LWZX 23
#define OP_31_XOP_TRAP_64 68
#define OP_31_XOP_DCBF 86
#define OP_31_XOP_LBZX 87
#define OP_31_XOP_STWX 151
#define OP_31_XOP_STBX 215
@ -374,6 +375,7 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs);
break;
case OP_31_XOP_DCBF:
case OP_31_XOP_DCBI:
/* Do nothing. The guest is performing dcbi because
* hardware DMA is not snooped by the dcache, but

6
arch/x86/kernel/cpu/perf_event.c
View File

@ -340,9 +340,6 @@ int x86_setup_perfctr(struct perf_event *event)
/* BTS is currently only allowed for user-mode. */
if (!attr->exclude_kernel)
return -EOPNOTSUPP;
if (!attr->exclude_guest)
return -EOPNOTSUPP;
}
hwc->config |= config;
@ -385,9 +382,6 @@ int x86_pmu_hw_config(struct perf_event *event)
if (event->attr.precise_ip) {
int precise = 0;
if (!event->attr.exclude_guest)
return -EOPNOTSUPP;
/* Support for constant skid */
if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
precise++;

1
arch/x86/kernel/entry_32.S
View File

@ -1065,7 +1065,6 @@ ENTRY(xen_failsafe_callback)
lea 16(%esp),%esp
CFI_ADJUST_CFA_OFFSET -16
jz 5f
addl $16,%esp
jmp iret_exc
5: pushl_cfi $-1 /* orig_ax = -1 => not a system call */
SAVE_ALL

9
arch/x86/kernel/step.c
View File

@ -165,10 +165,11 @@ void set_task_blockstep(struct task_struct *task, bool on)
* Ensure irq/preemption can't change debugctl in between.
* Note also that both TIF_BLOCKSTEP and debugctl should
* be changed atomically wrt preemption.
* FIXME: this means that set/clear TIF_BLOCKSTEP is simply
* wrong if task != current, SIGKILL can wakeup the stopped
* tracee and set/clear can play with the running task, this
* can confuse the next __switch_to_xtra().
*
* NOTE: this means that set/clear TIF_BLOCKSTEP is only safe if
* task is current or it can't be running, otherwise we can race
* with __switch_to_xtra(). We rely on ptrace_freeze_traced() but
* PTRACE_KILL is not safe.
*/
local_irq_disable();
debugctl = get_debugctlmsr();

7
arch/x86/xen/smp.c
View File

@ -432,13 +432,6 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */
play_dead_common();
HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
cpu_bringup();
/*
* Balance out the preempt calls - as we are running in cpu_idle
* loop which has been called at bootup from cpu_bringup_and_idle.
* The cpucpu_bringup_and_idle called cpu_bringup which made a
* preempt_disable() So this preempt_enable will balance it out.
*/
preempt_enable();
}
#else /* !CONFIG_HOTPLUG_CPU */

3
drivers/acpi/apei/apei-base.c
View File

@ -590,6 +590,9 @@ static int apei_check_gar(struct acpi_generic_address *reg, u64 *paddr,
if (bit_width == 32 && bit_offset == 0 && (*paddr & 0x03) == 0 &&
*access_bit_width < 32)
*access_bit_width = 32;
else if (bit_width == 64 && bit_offset == 0 && (*paddr & 0x07) == 0 &&
*access_bit_width < 64)
*access_bit_width = 64;
if ((bit_width + bit_offset) > *access_bit_width) {
pr_warning(FW_BUG APEI_PFX

4
drivers/acpi/processor_idle.c
View File

@ -958,6 +958,9 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr)
return -EINVAL;
}
if (!dev)
return -EINVAL;
dev->cpu = pr->id;
if (max_cstate == 0)
@ -1149,6 +1152,7 @@ int acpi_processor_cst_has_changed(struct acpi_processor *pr)
}
/* Populate Updated C-state information */
acpi_processor_get_power_info(pr);
acpi_processor_setup_cpuidle_states(pr);
/* Enable all cpuidle devices */

7
drivers/acpi/processor_perflib.c
View File

@ -340,6 +340,13 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10)
|| boot_cpu_data.x86 == 0x11) {
rdmsr(MSR_AMD_PSTATE_DEF_BASE + index, lo, hi);
/*
* MSR C001_0064+:
* Bit 63: PstateEn. Read-write. If set, the P-state is valid.
*/
if (!(hi & BIT(31)))
return;
fid = lo & 0x3f;
did = (lo >> 6) & 7;
if (boot_cpu_data.x86 == 0x10)

8
drivers/ata/ahci.c
View File

@ -53,6 +53,7 @@
enum {
AHCI_PCI_BAR_STA2X11 = 0,
AHCI_PCI_BAR_ENMOTUS = 2,
AHCI_PCI_BAR_STANDARD = 5,
};
@ -410,6 +411,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
/* Enmotus */
{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
/* Generic, PCI class code for AHCI */
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
@ -1098,9 +1102,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
dev_info(&pdev->dev,
"PDC42819 can only drive SATA devices with this driver\n");
/* The Connext uses non-standard BAR */
/* Both Connext and Enmotus devices use non-standard BARs */
if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
/* acquire resources */
rc = pcim_enable_device(pdev);

6
drivers/ata/libahci.c
View File

@ -1951,13 +1951,13 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
/* Use the nominal value 10 ms if the read MDAT is zero,
* the nominal value of DETO is 20 ms.
*/
if (dev->sata_settings[ATA_LOG_DEVSLP_VALID] &
if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
ATA_LOG_DEVSLP_VALID_MASK) {
mdat = dev->sata_settings[ATA_LOG_DEVSLP_MDAT] &
mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
ATA_LOG_DEVSLP_MDAT_MASK;
if (!mdat)
mdat = 10;
deto = dev->sata_settings[ATA_LOG_DEVSLP_DETO];
deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
if (!deto)
deto = 20;
} else {

22
drivers/ata/libata-core.c
View File

@ -2325,24 +2325,28 @@ int ata_dev_configure(struct ata_device *dev)
}
}
/* check and mark DevSlp capability */
if (ata_id_has_devslp(dev->id))
dev->flags |= ATA_DFLAG_DEVSLP;
/* Obtain SATA Settings page from Identify Device Data Log,
* which contains DevSlp timing variables etc.
* Exclude old devices with ata_id_has_ncq()
/* Check and mark DevSlp capability. Get DevSlp timing variables
* from SATA Settings page of Identify Device Data Log.
*/
if (ata_id_has_ncq(dev->id)) {
if (ata_id_has_devslp(dev->id)) {
u8 sata_setting[ATA_SECT_SIZE];
int i, j;
dev->flags |= ATA_DFLAG_DEVSLP;
err_mask = ata_read_log_page(dev,
ATA_LOG_SATA_ID_DEV_DATA,
ATA_LOG_SATA_SETTINGS,
dev->sata_settings,
sata_setting,
1);
if (err_mask)
ata_dev_dbg(dev,
"failed to get Identify Device Data, Emask 0x%x\n",
err_mask);
else
for (i = 0; i < ATA_LOG_DEVSLP_SIZE; i++) {
j = ATA_LOG_DEVSLP_OFFSET + i;
dev->devslp_timing[i] = sata_setting[j];
}
}
dev->cdb_len = 16;

2
drivers/ata/libata-eh.c
View File

@ -2094,7 +2094,7 @@ static unsigned int ata_eh_speed_down(struct ata_device *dev,
*/
static inline int ata_eh_worth_retry(struct ata_queued_cmd *qc)
{
if (qc->flags & AC_ERR_MEDIA)
if (qc->err_mask & AC_ERR_MEDIA)
return 0; /* don't retry media errors */
if (qc->flags & ATA_QCFLAG_IO)
return 1; /* otherwise retry anything from fs stack */

2
drivers/base/regmap/regmap-debugfs.c
View File

@ -121,8 +121,6 @@ static unsigned int regmap_debugfs_get_dump_start(struct regmap *map,
c->max = p - 1;
list_add_tail(&c->list,
&map->debugfs_off_cache);
} else {
return base;
}
/*

2
drivers/base/regmap/regmap.c
View File

@ -1106,7 +1106,7 @@ EXPORT_SYMBOL_GPL(regmap_raw_write);
* @val_count: Number of registers to write
*
* This function is intended to be used for writing a large block of
* data to be device either in single transfer or multiple transfer.
* data to the device either in single transfer or multiple transfer.
*
* A value of zero will be returned on success, a negative errno will
* be returned in error cases.

7
drivers/block/virtio_blk.c
View File

@ -889,6 +889,7 @@ static void virtblk_remove(struct virtio_device *vdev)
{
struct virtio_blk *vblk = vdev->priv;
int index = vblk->index;
int refc;
/* Prevent config work handler from accessing the device. */
mutex_lock(&vblk->config_lock);
@ -903,11 +904,15 @@ static void virtblk_remove(struct virtio_device *vdev)
flush_work(&vblk->config_work);
refc = atomic_read(&disk_to_dev(vblk->disk)->kobj.kref.refcount);
put_disk(vblk->disk);
mempool_destroy(vblk->pool);
vdev->config->del_vqs(vdev);
kfree(vblk);
ida_simple_remove(&vd_index_ida, index);
/* Only free device id if we don't have any users */
if (refc == 1)
ida_simple_remove(&vd_index_ida, index);
}
#ifdef CONFIG_PM

9
drivers/clk/mvebu/clk-cpu.c
View File

@ -124,7 +124,7 @@ void __init of_cpu_clk_setup(struct device_node *node)
clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
if (WARN_ON(!clks))
return;
goto clks_out;
for_each_node_by_type(dn, "cpu") {
struct clk_init_data init;
@ -134,11 +134,11 @@ void __init of_cpu_clk_setup(struct device_node *node)
int cpu, err;
if (WARN_ON(!clk_name))
return;
goto bail_out;
err = of_property_read_u32(dn, "reg", &cpu);
if (WARN_ON(err))
return;
goto bail_out;
sprintf(clk_name, "cpu%d", cpu);
parent_clk = of_clk_get(node, 0);
@ -167,6 +167,9 @@ void __init of_cpu_clk_setup(struct device_node *node)
return;
bail_out:
kfree(clks);
while(ncpus--)
kfree(cpuclk[ncpus].clk_name);
clks_out:
kfree(cpuclk);
}

2
drivers/cpufreq/Kconfig.x86
View File

@ -106,7 +106,7 @@ config X86_POWERNOW_K7_ACPI
config X86_POWERNOW_K8
tristate "AMD Opteron/Athlon64 PowerNow!"
select CPU_FREQ_TABLE
depends on ACPI && ACPI_PROCESSOR
depends on ACPI && ACPI_PROCESSOR && X86_ACPI_CPUFREQ
help
This adds the CPUFreq driver for K8/early Opteron/Athlon64 processors.
Support for K10 and newer processors is now in acpi-cpufreq.

7
drivers/cpufreq/acpi-cpufreq.c
View File

@ -1030,4 +1030,11 @@ MODULE_PARM_DESC(acpi_pstate_strict,
late_initcall(acpi_cpufreq_init);
module_exit(acpi_cpufreq_exit);
static const struct x86_cpu_id acpi_cpufreq_ids[] = {
X86_FEATURE_MATCH(X86_FEATURE_ACPI),
X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE),
{}
};
MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids);
MODULE_ALIAS("acpi");

5
drivers/cpufreq/cpufreq-cpu0.c
View File

@ -71,12 +71,15 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
}
if (cpu_reg) {
rcu_read_lock();
opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
if (IS_ERR(opp)) {
rcu_read_unlock();
pr_err("failed to find OPP for %ld\n", freq_Hz);
return PTR_ERR(opp);
}
volt = opp_get_voltage(opp);
rcu_read_unlock();
tol = volt * voltage_tolerance / 100;
volt_old = regulator_get_voltage(cpu_reg);
}
@ -236,12 +239,14 @@ static int cpu0_cpufreq_driver_init(void)
*/
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
;
rcu_read_lock();
opp = opp_find_freq_exact(cpu_dev,
freq_table[0].frequency * 1000, true);
min_uV = opp_get_voltage(opp);
opp = opp_find_freq_exact(cpu_dev,
freq_table[i-1].frequency * 1000, true);
max_uV = opp_get_voltage(opp);
rcu_read_unlock();
ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
if (ret > 0)
transition_latency += ret * 1000;

3
drivers/cpufreq/omap-cpufreq.c
View File

@ -110,13 +110,16 @@ static int omap_target(struct cpufreq_policy *policy,
freq = ret;
if (mpu_reg) {
rcu_read_lock();
opp = opp_find_freq_ceil(mpu_dev, &freq);
if (IS_ERR(opp)) {
rcu_read_unlock();
dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
__func__, freqs.new);
return -EINVAL;
}
volt = opp_get_voltage(opp);
rcu_read_unlock();
tol = volt * OPP_TOLERANCE / 100;
volt_old = regulator_get_voltage(mpu_reg);
}

5
drivers/devfreq/devfreq.c
View File

@ -994,6 +994,11 @@ module_exit(devfreq_exit);
* @freq: The frequency given to target function
* @flags: Flags handed from devfreq framework.
*
* Locking: This function must be called under rcu_read_lock(). opp is a rcu
* protected pointer. The reason for the same is that the opp pointer which is
* returned will remain valid for use with opp_get_{voltage, freq} only while
* under the locked area. The pointer returned must be used prior to unlocking
* with rcu_read_unlock() to maintain the integrity of the pointer.
*/
struct opp *devfreq_recommended_opp(struct device *dev, unsigned long *freq,
u32 flags)

94
drivers/devfreq/exynos4_bus.c
View File

@ -73,6 +73,16 @@ enum busclk_level_idx {
#define EX4210_LV_NUM (LV_2 + 1)
#define EX4x12_LV_NUM (LV_4 + 1)
/**
* struct busfreq_opp_info - opp information for bus
* @rate: Frequency in hertz
* @volt: Voltage in microvolts corresponding to this OPP
*/
struct busfreq_opp_info {
unsigned long rate;
unsigned long volt;
};
struct busfreq_data {
enum exynos4_busf_type type;
struct device *dev;
@ -80,7 +90,7 @@ struct busfreq_data {
bool disabled;
struct regulator *vdd_int;
struct regulator *vdd_mif; /* Exynos4412/4212 only */
struct opp *curr_opp;
struct busfreq_opp_info curr_oppinfo;
struct exynos4_ppmu dmc[2];
struct notifier_block pm_notifier;
@ -296,13 +306,14 @@ static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
};
static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
static int exynos4210_set_busclk(struct busfreq_data *data,
struct busfreq_opp_info *oppi)
{
unsigned int index;
unsigned int tmp;
for (index = LV_0; index < EX4210_LV_NUM; index++)
if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk)
if (oppi->rate == exynos4210_busclk_table[index].clk)
break;
if (index == EX4210_LV_NUM)
@ -361,13 +372,14 @@ static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
return 0;
}
static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
static int exynos4x12_set_busclk(struct busfreq_data *data,
struct busfreq_opp_info *oppi)
{
unsigned int index;
unsigned int tmp;
for (index = LV_0; index < EX4x12_LV_NUM; index++)
if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk)
if (oppi->rate == exynos4x12_mifclk_table[index].clk)
break;
if (index == EX4x12_LV_NUM)
@ -576,11 +588,12 @@ static int exynos4x12_get_intspec(unsigned long mifclk)
return -EINVAL;
}
static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
struct opp *oldopp)
static int exynos4_bus_setvolt(struct busfreq_data *data,
struct busfreq_opp_info *oppi,
struct busfreq_opp_info *oldoppi)
{
int err = 0, tmp;
unsigned long volt = opp_get_voltage(opp);
unsigned long volt = oppi->volt;
switch (data->type) {
case TYPE_BUSF_EXYNOS4210:
@ -595,11 +608,11 @@ static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
if (err)
break;
tmp = exynos4x12_get_intspec(opp_get_freq(opp));
tmp = exynos4x12_get_intspec(oppi->rate);
if (tmp < 0) {
err = tmp;
regulator_set_voltage(data->vdd_mif,
opp_get_voltage(oldopp),
oldoppi->volt,
MAX_SAFEVOLT);
break;
}
@ -609,7 +622,7 @@ static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
/* Try to recover */
if (err)
regulator_set_voltage(data->vdd_mif,
opp_get_voltage(oldopp),
oldoppi->volt,
MAX_SAFEVOLT);
break;
default:
@ -626,17 +639,26 @@ static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
struct platform_device *pdev = container_of(dev, struct platform_device,
dev);
struct busfreq_data *data = platform_get_drvdata(pdev);
struct opp *opp = devfreq_recommended_opp(dev, _freq, flags);
unsigned long freq = opp_get_freq(opp);
unsigned long old_freq = opp_get_freq(data->curr_opp);
struct opp *opp;
unsigned long freq;
unsigned long old_freq = data->curr_oppinfo.rate;
struct busfreq_opp_info new_oppinfo;
if (IS_ERR(opp))
rcu_read_lock();
opp = devfreq_recommended_opp(dev, _freq, flags);
if (IS_ERR(opp)) {
rcu_read_unlock();
return PTR_ERR(opp);
}
new_oppinfo.rate = opp_get_freq(opp);
new_oppinfo.volt = opp_get_voltage(opp);
rcu_read_unlock();
freq = new_oppinfo.rate;
if (old_freq == freq)
return 0;
dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp));
dev_dbg(dev, "targetting %lukHz %luuV\n", freq, new_oppinfo.volt);
mutex_lock(&data->lock);
@ -644,17 +666,18 @@ static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
goto out;
if (old_freq < freq)
err = exynos4_bus_setvolt(data, opp, data->curr_opp);
err = exynos4_bus_setvolt(data, &new_oppinfo,
&data->curr_oppinfo);
if (err)
goto out;
if (old_freq != freq) {
switch (data->type) {
case TYPE_BUSF_EXYNOS4210:
err = exynos4210_set_busclk(data, opp);
err = exynos4210_set_busclk(data, &new_oppinfo);
break;
case TYPE_BUSF_EXYNOS4x12:
err = exynos4x12_set_busclk(data, opp);
err = exynos4x12_set_busclk(data, &new_oppinfo);
break;
default:
err = -EINVAL;
@ -664,11 +687,12 @@ static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
goto out;
if (old_freq > freq)
err = exynos4_bus_setvolt(data, opp, data->curr_opp);
err = exynos4_bus_setvolt(data, &new_oppinfo,
&data->curr_oppinfo);
if (err)
goto out;
data->curr_opp = opp;
data->curr_oppinfo = new_oppinfo;
out:
mutex_unlock(&data->lock);
return err;
@ -702,7 +726,7 @@ static int exynos4_bus_get_dev_status(struct device *dev,
exynos4_read_ppmu(data);
busier_dmc = exynos4_get_busier_dmc(data);
stat->current_frequency = opp_get_freq(data->curr_opp);
stat->current_frequency = data->curr_oppinfo.rate;
if (busier_dmc)
addr = S5P_VA_DMC1;
@ -933,6 +957,7 @@ static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
struct busfreq_data *data = container_of(this, struct busfreq_data,
pm_notifier);
struct opp *opp;
struct busfreq_opp_info new_oppinfo;
unsigned long maxfreq = ULONG_MAX;
int err = 0;
@ -943,18 +968,29 @@ static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
data->disabled = true;
rcu_read_lock();
opp = opp_find_freq_floor(data->dev, &maxfreq);
if (IS_ERR(opp)) {
rcu_read_unlock();
dev_err(data->dev, "%s: unable to find a min freq\n",
__func__);
return PTR_ERR(opp);
}
new_oppinfo.rate = opp_get_freq(opp);
new_oppinfo.volt = opp_get_voltage(opp);
rcu_read_unlock();
err = exynos4_bus_setvolt(data, opp, data->curr_opp);
err = exynos4_bus_setvolt(data, &new_oppinfo,
&data->curr_oppinfo);
if (err)
goto unlock;
switch (data->type) {
case TYPE_BUSF_EXYNOS4210:
err = exynos4210_set_busclk(data, opp);
err = exynos4210_set_busclk(data, &new_oppinfo);
break;
case TYPE_BUSF_EXYNOS4x12:
err = exynos4x12_set_busclk(data, opp);
err = exynos4x12_set_busclk(data, &new_oppinfo);
break;
default:
err = -EINVAL;
@ -962,7 +998,7 @@ static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
if (err)
goto unlock;
data->curr_opp = opp;
data->curr_oppinfo = new_oppinfo;
unlock:
mutex_unlock(&data->lock);
if (err)
@ -1027,13 +1063,17 @@ static int exynos4_busfreq_probe(struct platform_device *pdev)
}
}
rcu_read_lock();
opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq);
if (IS_ERR(opp)) {
rcu_read_unlock();
dev_err(dev, "Invalid initial frequency %lu kHz.\n",
exynos4_devfreq_profile.initial_freq);
return PTR_ERR(opp);
}
data->curr_opp = opp;
data->curr_oppinfo.rate = opp_get_freq(opp);
data->curr_oppinfo.volt = opp_get_voltage(opp);
rcu_read_unlock();
platform_set_drvdata(pdev, data);

5
drivers/dma/imx-dma.c
View File

@ -685,9 +685,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
break;
}
imxdmac->hw_chaining = 1;
if (!imxdma_hw_chain(imxdmac))
return -EINVAL;
imxdmac->hw_chaining = 0;
imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
CCR_REN;

2
drivers/dma/ioat/dma_v3.c
View File

@ -951,7 +951,7 @@ static int ioat_xor_val_self_test(struct ioatdma_device *device)
goto free_resources;
}
}
dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE);
dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
/* skip validate if the capability is not present */
if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))

8
drivers/dma/tegra20-apb-dma.c
View File

@ -267,6 +267,7 @@ static struct tegra_dma_desc *tegra_dma_desc_get(
if (async_tx_test_ack(&dma_desc->txd)) {
list_del(&dma_desc->node);
spin_unlock_irqrestore(&tdc->lock, flags);
dma_desc->txd.flags = 0;
return dma_desc;
}
}
@ -1051,7 +1052,9 @@ struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
csr |= TEGRA_APBDMA_CSR_FLOW | TEGRA_APBDMA_CSR_IE_EOC;
csr |= TEGRA_APBDMA_CSR_FLOW;
if (flags & DMA_PREP_INTERRUPT)
csr |= TEGRA_APBDMA_CSR_IE_EOC;
csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
@ -1096,7 +1099,8 @@ struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
mem += len;
}
sg_req->last_sg = true;
dma_desc->txd.flags = 0;
if (flags & DMA_CTRL_ACK)
dma_desc->txd.flags = DMA_CTRL_ACK;
/*
* Make sure that mode should not be conflicting with currently

12
drivers/gpio/gpio-mvebu.c
View File

@ -546,10 +546,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
spin_lock_init(&mvchip->lock);
mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mvchip->membase)) {
kfree(mvchip->chip.label);
if (IS_ERR(mvchip->membase))
return PTR_ERR(mvchip->membase);
}
/* The Armada XP has a second range of registers for the
* per-CPU registers */
@ -557,16 +555,13 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (! res) {
dev_err(&pdev->dev, "Cannot get memory resource\n");
kfree(mvchip->chip.label);
return -ENODEV;
}
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
res);
if (IS_ERR(mvchip->percpu_membase)) {
kfree(mvchip->chip.label);
if (IS_ERR(mvchip->percpu_membase))
return PTR_ERR(mvchip->percpu_membase);
}
}
/*
@ -625,7 +620,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
if (mvchip->irqbase < 0) {
dev_err(&pdev->dev, "no irqs\n");
kfree(mvchip->chip.label);
return -ENOMEM;
}
@ -633,7 +627,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip->membase, handle_level_irq);
if (! gc) {
dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
kfree(mvchip->chip.label);
return -ENOMEM;
}
@ -668,7 +661,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
IRQ_LEVEL | IRQ_NOPROBE);
kfree(gc);
kfree(mvchip->chip.label);
return -ENODEV;
}

14
drivers/gpio/gpio-samsung.c
View File

@ -32,7 +32,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
@ -446,7 +445,7 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
};
#endif
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
static struct samsung_gpio_cfg exynos_gpio_cfg = {
.set_pull = exynos_gpio_setpull,
.get_pull = exynos_gpio_getpull,
@ -2446,7 +2445,7 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
};
#endif
#ifdef CONFIG_ARCH_EXYNOS5
#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_1[] = {
{
.chip = {
@ -2614,7 +2613,7 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
};
#endif
#ifdef CONFIG_ARCH_EXYNOS5
#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_2[] = {
{
.chip = {
@ -2675,7 +2674,7 @@ static struct samsung_gpio_chip exynos5_gpios_2[] = {
};
#endif
#ifdef CONFIG_ARCH_EXYNOS5
#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_3[] = {
{
.chip = {
@ -2711,7 +2710,7 @@ static struct samsung_gpio_chip exynos5_gpios_3[] = {
};
#endif
#ifdef CONFIG_ARCH_EXYNOS5
#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_4[] = {
{
.chip = {
@ -3010,7 +3009,7 @@ static __init int samsung_gpiolib_init(void)
int i, nr_chips;
int group = 0;
#ifdef CONFIG_PINCTRL_SAMSUNG
#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
/*
* This gpio driver includes support for device tree support and there
* are platforms using it. In order to maintain compatibility with those
@ -3026,6 +3025,7 @@ static __init int samsung_gpiolib_init(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,pinctrl-exynos4210", },
{ .compatible = "samsung,pinctrl-exynos4x12", },
{ .compatible = "samsung,pinctrl-exynos5440", },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np && of_device_is_available(pctrl_np))

3
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -641,6 +641,7 @@ static void i915_ring_error_state(struct seq_file *m,
seq_printf(m, "%s command stream:\n", ring_str(ring));
seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
seq_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
@ -693,6 +694,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
seq_printf(m, "EIR: 0x%08x\n", error->eir);
seq_printf(m, "IER: 0x%08x\n", error->ier);
seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
seq_printf(m, "CCID: 0x%08x\n", error->ccid);
for (i = 0; i < dev_priv->num_fence_regs; i++)

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -188,10 +188,13 @@ struct drm_i915_error_state {
u32 pgtbl_er;
u32 ier;
u32 ccid;
u32 derrmr;
u32 forcewake;
bool waiting[I915_NUM_RINGS];
u32 pipestat[I915_MAX_PIPES];
u32 tail[I915_NUM_RINGS];
u32 head[I915_NUM_RINGS];
u32 ctl[I915_NUM_RINGS];
u32 ipeir[I915_NUM_RINGS];
u32 ipehr[I915_NUM_RINGS];
u32 instdone[I915_NUM_RINGS];

21
drivers/gpu/drm/i915/i915_gem_execbuffer.c
View File

@ -539,6 +539,8 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
total = 0;
for (i = 0; i < count; i++) {
struct drm_i915_gem_relocation_entry __user *user_relocs;
u64 invalid_offset = (u64)-1;
int j;
user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
@ -549,6 +551,25 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
goto err;
}
/* As we do not update the known relocation offsets after
* relocating (due to the complexities in lock handling),
* we need to mark them as invalid now so that we force the
* relocation processing next time. Just in case the target
* object is evicted and then rebound into its old
* presumed_offset before the next execbuffer - if that
* happened we would make the mistake of assuming that the
* relocations were valid.
*/
for (j = 0; j < exec[i].relocation_count; j++) {
if (copy_to_user(&user_relocs[j].presumed_offset,
&invalid_offset,
sizeof(invalid_offset))) {
ret = -EFAULT;
mutex_lock(&dev->struct_mutex);
goto err;
}
}
reloc_offset[i] = total;
total += exec[i].relocation_count;
}

11
drivers/gpu/drm/i915/i915_irq.c
View File

@ -1157,6 +1157,7 @@ static void i915_record_ring_state(struct drm_device *dev,
error->acthd[ring->id] = intel_ring_get_active_head(ring);
error->head[ring->id] = I915_READ_HEAD(ring);
error->tail[ring->id] = I915_READ_TAIL(ring);
error->ctl[ring->id] = I915_READ_CTL(ring);
error->cpu_ring_head[ring->id] = ring->head;
error->cpu_ring_tail[ring->id] = ring->tail;
@ -1251,6 +1252,16 @@ static void i915_capture_error_state(struct drm_device *dev)
else
error->ier = I915_READ(IER);
if (INTEL_INFO(dev)->gen >= 6)
error->derrmr = I915_READ(DERRMR);
if (IS_VALLEYVIEW(dev))
error->forcewake = I915_READ(FORCEWAKE_VLV);
else if (INTEL_INFO(dev)->gen >= 7)
error->forcewake = I915_READ(FORCEWAKE_MT);
else if (INTEL_INFO(dev)->gen == 6)
error->forcewake = I915_READ(FORCEWAKE);
for_each_pipe(pipe)
error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));

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