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dt-bindings: phy: Fix node descriptions in uniphier-phy example

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Prior to adding dt-bindings for SoC-dependent controllers, rename the
phy nodes and their parent nodes to the generic names in the example.

And drop parent nodes of each phy as they are not directly necessary here.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]
Link: https://lore.kernel.org/r/20221213082449.2721-8-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Kunihiko Hayashi 2022-12-13 17:24:39 +09:00 committed by Rob Herring
parent a1e616a5fc
commit 4278eabebc
4 changed files with 43 additions and 71 deletions
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24
Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
View File

@ -117,20 +117,12 @@ additionalProperties: false
examples:
- |
ahci-glue@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci_phy: phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
};
ahci_phy: phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
};

35
Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
View File

@ -61,28 +61,23 @@ examples:
- |
// The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.
soc-glue@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
usb-hub {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
usb-controller {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
usb_phy0: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
usb_phy0: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
usb_phy1: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
usb_phy1: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
usb_phy2: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
usb_phy2: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
};

29
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
View File

@ -146,22 +146,15 @@ additionalProperties: false
examples:
- |
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_hsphy0: hs-phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
};
usb_hsphy0: phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
};

26
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
View File

@ -131,21 +131,13 @@ additionalProperties: false
examples:
- |
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_ssphy0: ss-phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
};
usb_ssphy0: phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
};