drm/rockchip: vop: add rk3188 vop definitions
The rk3188 has 2 vops not using iommus which only output directly to a rgb interface per vop. So all other output modes like hdmi are provided by external brige chips. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Sandy Huang <hjc@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180830110937.1739-1-heiko@sntech.de
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@ -10,6 +10,7 @@ Required properties:
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"rockchip,rk3126-vop";
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"rockchip,px30-vop-lit";
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"rockchip,px30-vop-big";
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"rockchip,rk3188-vop";
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"rockchip,rk3288-vop";
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"rockchip,rk3368-vop";
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"rockchip,rk3366-vop";
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@ -299,6 +299,93 @@ static const struct vop_data px30_vop_lit = {
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.win_size = ARRAY_SIZE(px30_vop_lit_win_data),
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};
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static const struct vop_scl_regs rk3188_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win_phy rk3188_win0_data = {
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.scl = &rk3188_win_scl,
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.data_formats = formats_win_full,
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.nformats = ARRAY_SIZE(formats_win_full),
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.enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
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.format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
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.rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
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.act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
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};
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static const struct vop_win_phy rk3188_win1_data = {
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.data_formats = formats_win_lite,
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.nformats = ARRAY_SIZE(formats_win_lite),
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.enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
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.format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
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.rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
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/* no act_info on window1 */
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.dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
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.dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
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.yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
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};
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static const struct vop_modeset rk3188_modeset = {
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.htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
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.hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
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.vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
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.vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
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};
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static const struct vop_output rk3188_output = {
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.pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
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};
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static const struct vop_common rk3188_common = {
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.gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
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.standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
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.out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
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.cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
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.dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24),
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};
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static const struct vop_win_data rk3188_vop_win_data[] = {
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{ .base = 0x00, .phy = &rk3188_win0_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x00, .phy = &rk3188_win1_data,
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.type = DRM_PLANE_TYPE_CURSOR },
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};
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static const int rk3188_vop_intrs[] = {
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0,
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FS_INTR,
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LINE_FLAG_INTR,
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BUS_ERROR_INTR,
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};
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static const struct vop_intr rk3188_vop_intr = {
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.intrs = rk3188_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3188_vop_intrs),
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.line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
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.status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
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.enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
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.clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
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};
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static const struct vop_data rk3188_vop = {
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.intr = &rk3188_vop_intr,
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.common = &rk3188_common,
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.modeset = &rk3188_modeset,
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.output = &rk3188_output,
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.win = rk3188_vop_win_data,
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.win_size = ARRAY_SIZE(rk3188_vop_win_data),
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.feature = VOP_FEATURE_INTERNAL_RGB,
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};
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static const struct vop_scl_extension rk3288_win_full_scl_ext = {
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.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
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.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
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@ -667,6 +754,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
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.data = &px30_vop_big },
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{ .compatible = "rockchip,px30-vop-lit",
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.data = &px30_vop_lit },
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{ .compatible = "rockchip,rk3188-vop",
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.data = &rk3188_vop },
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{ .compatible = "rockchip,rk3288-vop",
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.data = &rk3288_vop },
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{ .compatible = "rockchip,rk3368-vop",
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@ -958,4 +958,29 @@
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#define PX30_GAMMA_LUT_ADDR 0x00a00
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/* px30 register definition end */
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/* rk3188 register definition */
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#define RK3188_SYS_CTRL 0x00
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#define RK3188_DSP_CTRL0 0x04
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#define RK3188_DSP_CTRL1 0x08
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#define RK3188_INT_STATUS 0x10
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#define RK3188_WIN0_YRGB_MST0 0x20
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#define RK3188_WIN0_CBR_MST0 0x24
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#define RK3188_WIN0_YRGB_MST1 0x28
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#define RK3188_WIN0_CBR_MST1 0x2c
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#define RK3188_WIN_VIR 0x30
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#define RK3188_WIN0_ACT_INFO 0x34
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#define RK3188_WIN0_DSP_INFO 0x38
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#define RK3188_WIN0_DSP_ST 0x3c
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#define RK3188_WIN0_SCL_FACTOR_YRGB 0x40
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#define RK3188_WIN0_SCL_FACTOR_CBR 0x44
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#define RK3188_WIN1_MST 0x4c
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#define RK3188_WIN1_DSP_INFO 0x50
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#define RK3188_WIN1_DSP_ST 0x54
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#define RK3188_DSP_HTOTAL_HS_END 0x6c
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#define RK3188_DSP_HACT_ST_END 0x70
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#define RK3188_DSP_VTOTAL_VS_END 0x74
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#define RK3188_DSP_VACT_ST_END 0x78
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#define RK3188_REG_CFG_DONE 0x90
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/* rk3188 register definition end */
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#endif /* _ROCKCHIP_VOP_REG_H */
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