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pinctrl: sirf: fix the pin number and mux bit for usp0

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we missed a pin and related mux bit for usp pin group, this
patch fixes it.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Qipan Li 2013-07-04 15:55:25 +08:00 committed by Linus Walleij
parent c5f167d315
commit 42a708c932
1 changed files with 2 additions and 2 deletions
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4
drivers/pinctrl/sirf/pinctrl-atlas6.c
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@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = { static const struct sirfsoc_muxmask usp0_muxmask[] = {
{ {
.group = 1, .group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
}, },
}; };
@ -507,7 +507,7 @@ static const struct sirfsoc_padmux usp0_padmux = {
.funcval = 0, .funcval = 0,
}; };
static const unsigned usp0_pins[] = { 51, 52, 53, 54 }; static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp1_muxmask[] = { static const struct sirfsoc_muxmask usp1_muxmask[] = {
{ {