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drm/amd/powerplay/vega20: tell the correct gfx voltage V2

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Export the correct gfx voltage by hwmon interface.

V2: update the register naming for consistency

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2018-09-17 18:41:28 +08:00 committed by Alex Deucher
parent 3546916f42
commit 42fae99520
3 changed files with 18 additions and 0 deletions
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3
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
View File

@ -175,4 +175,7 @@
#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
#define mmSMUSVI0_PLANE0_CURRENTVID 0x0013
#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
#define mmSMUSVI0_TEL_PLANE0 0x0004
#endif

3
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
View File

@ -258,4 +258,7 @@
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
#endif

12
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
View File

@ -46,6 +46,9 @@
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
#include "soc15_common.h"
#include "smuio/smuio_9_0_offset.h"
#include "smuio/smuio_9_0_sh_mask.h"
static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
{
@ -1915,6 +1918,8 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
struct amdgpu_device *adev = hwmgr->adev;
uint32_t val_vid;
int ret = 0;
switch (idx) {
@ -1949,6 +1954,13 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*size = 16;
ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
break;
case AMDGPU_PP_SENSOR_VDDGFX:
val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
*((uint32_t *)value) =
(uint32_t)convert_to_vddc((uint8_t)val_vid);
break;
case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
if (!ret)