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drm/amd/display: Update viewport position for phantom pipes

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[Description]
In some cases the viewport position of the main pipes can change without
triggering a full update. In this case the subvp phantom viewports must
be updated accordingly.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee 2022-08-25 16:04:29 -04:00 committed by Alex Deucher
parent 39fc82b7e0
commit 43080c9b75
5 changed files with 47 additions and 2 deletions
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7
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -1898,8 +1898,11 @@ void dcn20_post_unlock_program_front_end(
* can underflow due to HUBP_VTG_SEL programming if done in the regular front end
* programming sequence).
*/
if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
dcn20_program_pipe(dc, pipe, context);
if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
if (dc->hwss.update_phantom_vp_position)
dc->hwss.update_phantom_vp_position(dc, context, pipe);
dcn20_program_pipe(dc, pipe, context);
}
}
}

32
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
View File

@ -1301,3 +1301,35 @@ void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
} else
BREAK_TO_DEBUGGER();
}
/* For SubVP the main pipe can have a viewport position change
* without a full update. In this case we must also update the
* viewport positions for the phantom pipe accordingly.
*/
void dcn32_update_phantom_vp_position(struct dc *dc,
struct dc_state *context,
struct pipe_ctx *phantom_pipe)
{
uint8_t i;
struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) {
if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
phantom_pipe->plane_state->update_flags.bits.position_change = 1;
resource_build_scaling_params(phantom_pipe);
return;
}
}
}
}

4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
View File

@ -87,4 +87,8 @@ bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
enum phy_state target_state);
void dcn32_update_phantom_vp_position(struct dc *dc,
struct dc_state *context,
struct pipe_ctx *phantom_pipe);
#endif /* __DC_HWSS_DCN32_H__ */

1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
View File

@ -105,6 +105,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
.update_visual_confirm_color = dcn20_update_visual_confirm_color,
.update_phy_state = dcn32_update_phy_state,
.update_phantom_vp_position = dcn32_update_phantom_vp_position,
};
static const struct hwseq_private_funcs dcn32_private_funcs = {

5
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -247,6 +247,11 @@ struct hw_sequencer_funcs {
void (*update_phy_state)(struct dc_state *state, struct pipe_ctx *pipe_ctx, enum phy_state target_state);
void (*update_phantom_vp_position)(struct dc *dc,
struct dc_state *context,
struct pipe_ctx *phantom_pipe);
void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
void (*subvp_pipe_control_lock)(struct dc *dc,
struct dc_state *context,