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arm64: dts: imx8: add lsio lpcg clocks

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Add lsio lpcg clocks

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Dong Aisheng 2021-03-08 11:14:20 +08:00 committed by Shawn Guo
parent 0dcd27bda2
commit 438ae46b8e
1 changed files with 155 additions and 1 deletions
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156
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
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@ -4,12 +4,29 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "lsio_mem_clk";
};
lsio_bus_clk: clock-lsio-bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "lsio_bus_clk";
};
lsio_gpio0: gpio@5d080000 {
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@ -131,8 +148,145 @@ lsio_subsys: bus@5d000000 {
power-domains = <&pd IMX_SC_R_MU_13A>;
};
lsio_lpcg: clock-controller@5d400000 {
/* LPCG clocks */
lsio_lpcg: clock-controller-legacy@5d400000 {
reg = <0x5d400000 0x400000>;
#clock-cells = <1>;
};
pwm0_lpcg: clock-controller@5d400000 {
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
<&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM0_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm0_lpcg_ipg_clk",
"pwm0_lpcg_ipg_hf_clk",
"pwm0_lpcg_ipg_s_clk",
"pwm0_lpcg_ipg_slv_clk",
"pwm0_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_0>;
};
pwm1_lpcg: clock-controller@5d410000 {
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
<&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM1_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm1_lpcg_ipg_clk",
"pwm1_lpcg_ipg_hf_clk",
"pwm1_lpcg_ipg_s_clk",
"pwm1_lpcg_ipg_slv_clk",
"pwm1_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_1>;
};
pwm2_lpcg: clock-controller@5d420000 {
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
<&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM2_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm2_lpcg_ipg_clk",
"pwm2_lpcg_ipg_hf_clk",
"pwm2_lpcg_ipg_s_clk",
"pwm2_lpcg_ipg_slv_clk",
"pwm2_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_2>;
};
pwm3_lpcg: clock-controller@5d430000 {
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
<&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM3_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm3_lpcg_ipg_clk",
"pwm3_lpcg_ipg_hf_clk",
"pwm3_lpcg_ipg_s_clk",
"pwm3_lpcg_ipg_slv_clk",
"pwm3_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_3>;
};
pwm4_lpcg: clock-controller@5d440000 {
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
<&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM4_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm4_lpcg_ipg_clk",
"pwm4_lpcg_ipg_hf_clk",
"pwm4_lpcg_ipg_s_clk",
"pwm4_lpcg_ipg_slv_clk",
"pwm4_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_4>;
};
pwm5_lpcg: clock-controller@5d450000 {
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
<&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM5_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm5_lpcg_ipg_clk",
"pwm5_lpcg_ipg_hf_clk",
"pwm5_lpcg_ipg_s_clk",
"pwm5_lpcg_ipg_slv_clk",
"pwm5_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_5>;
};
pwm6_lpcg: clock-controller@5d460000 {
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
<&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM6_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm6_lpcg_ipg_clk",
"pwm6_lpcg_ipg_hf_clk",
"pwm6_lpcg_ipg_s_clk",
"pwm6_lpcg_ipg_slv_clk",
"pwm6_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_6>;
};
pwm7_lpcg: clock-controller@5d470000 {
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
<&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM7_CLK>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm7_lpcg_ipg_clk",
"pwm7_lpcg_ipg_hf_clk",
"pwm7_lpcg_ipg_s_clk",
"pwm7_lpcg_ipg_slv_clk",
"pwm7_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_7>;
};
};