sh: hook up shared div4 clock code to sh7785
Hook up the shared 4-bit divisor clock code to sh7785. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
a1153e27ee
commit
43909a9380
@ -18,65 +18,14 @@
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#include <asm/freq.h>
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#include <cpu/sh7785.h>
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table cpg_div = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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struct clk_priv {
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unsigned int shift;
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/* allowable divisor bitmap */
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unsigned long div_bitmap;
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/* Supportable frequencies + termination entry */
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struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1];
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};
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#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \
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static struct clk_priv _name##_data = { \
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.shift = _shift, \
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.div_bitmap = _div_bitmap, \
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\
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.freq_table[0] = { \
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.index = 0, \
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.frequency = CPUFREQ_TABLE_END, \
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}, \
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}
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FRQMR_CLK_DATA(pfc, 0, 0x0f80);
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FRQMR_CLK_DATA(s3fc, 4, 0x0ff0);
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FRQMR_CLK_DATA(s2fc, 8, 0x0030);
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FRQMR_CLK_DATA(mfc, 12, 0x000c);
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FRQMR_CLK_DATA(bfc, 16, 0x0fe0);
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FRQMR_CLK_DATA(sfc, 20, 0x000c);
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FRQMR_CLK_DATA(ufc, 24, 0x000c);
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FRQMR_CLK_DATA(ifc, 28, 0x000e);
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static unsigned long frqmr_recalc(struct clk *clk)
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{
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struct clk_priv *data = clk->priv;
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unsigned int idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
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clk_rate_table_build(clk, data->freq_table, ARRAY_SIZE(div2),
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&cpg_div, &data->div_bitmap);
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return data->freq_table[idx].frequency;
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}
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static long frqmr_round_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_priv *data = clk->priv;
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return clk_rate_table_round(clk, data->freq_table, rate);
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}
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static struct clk_ops frqmr_clk_ops = {
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.recalc = frqmr_recalc,
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.round_rate = frqmr_round_rate,
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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static unsigned long pll_recalc(struct clk *clk)
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@ -92,16 +41,6 @@ static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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static struct clk pll_clk = {
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.name = "pll_clk",
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.id = -1,
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@ -110,87 +49,34 @@ static struct clk pll_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk cpu_clk = {
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.name = "cpu_clk", /* Ick */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &ifc_data,
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};
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static struct clk shyway_clk = {
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.name = "shyway_clk", /* SHck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &sfc_data,
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};
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static struct clk peripheral_clk = {
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.name = "peripheral_clk", /* Pck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &pfc_data,
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};
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static struct clk ddr_clk = {
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.name = "ddr_clk", /* DDRck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &mfc_data,
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};
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static struct clk bus_clk = {
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.name = "bus_clk", /* Bck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &bfc_data,
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};
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static struct clk ga_clk = {
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.name = "ga_clk", /* GAck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.priv = &s2fc_data,
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};
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static struct clk du_clk = {
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.name = "du_clk", /* DUck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.priv = &s3fc_data,
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};
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static struct clk umem_clk = {
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.name = "umem_clk", /* uck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &pll_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &ufc_data,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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&cpu_clk,
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­way_clk,
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&peripheral_clk,
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&ddr_clk,
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&bus_clk,
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&ga_clk,
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&du_clk,
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&umem_clk,
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};
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table div4_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
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DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_str, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
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[DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
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[DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
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[DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc80030
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@ -198,22 +84,22 @@ static struct clk *clks[] = {
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static struct clk mstp_clks[] = {
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/* MSTPCR0 */
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SH_CLK_MSTP32("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
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SH_CLK_MSTP32("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
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SH_CLK_MSTP32("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
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SH_CLK_MSTP32("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
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SH_CLK_MSTP32("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
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SH_CLK_MSTP32("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
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SH_CLK_MSTP32("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
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SH_CLK_MSTP32("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
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SH_CLK_MSTP32("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
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SH_CLK_MSTP32("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
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SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
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SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
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SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
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SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
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SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
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SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
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SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
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SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
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SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
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SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
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/* MSTPCR1 */
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SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
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@ -230,6 +116,9 @@ int __init arch_clk_init(void)
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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