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drm/radeon: expose render backend mask to the userspace

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This will allow userspace to correctly program the PA_SC_RASTER_CONFIG
register, so it can be considered a fix.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Marek Olšák 2013-12-22 02:18:01 +01:00 committed by Alex Deucher
parent 9fadb352ed
commit 439a1cfffe
5 changed files with 17 additions and 2 deletions
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2
drivers/gpu/drm/radeon/cik.c
View File

@ -3114,6 +3114,8 @@ static void cik_setup_rb(struct radeon_device *rdev,
mask <<= 1; mask <<= 1;
} }
rdev->config.cik.backend_enable_mask = enabled_rbs;
for (i = 0; i < se_num; i++) { for (i = 0; i < se_num; i++) {
cik_select_se_sh(rdev, i, 0xffffffff); cik_select_se_sh(rdev, i, 0xffffffff);
data = 0; data = 0;

4
drivers/gpu/drm/radeon/radeon.h
View File

@ -1940,7 +1940,7 @@ struct si_asic {
unsigned sc_earlyz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size;
unsigned num_tile_pipes; unsigned num_tile_pipes;
unsigned num_backends_per_se; unsigned backend_enable_mask;
unsigned backend_disable_mask_per_asic; unsigned backend_disable_mask_per_asic;
unsigned backend_map; unsigned backend_map;
unsigned num_texture_channel_caches; unsigned num_texture_channel_caches;
@ -1970,7 +1970,7 @@ struct cik_asic {
unsigned sc_earlyz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size;
unsigned num_tile_pipes; unsigned num_tile_pipes;
unsigned num_backends_per_se; unsigned backend_enable_mask;
unsigned backend_disable_mask_per_asic; unsigned backend_disable_mask_per_asic;
unsigned backend_map; unsigned backend_map;
unsigned num_texture_channel_caches; unsigned num_texture_channel_caches;

9
drivers/gpu/drm/radeon/radeon_kms.c
View File

@ -461,6 +461,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case RADEON_INFO_SI_CP_DMA_COMPUTE: case RADEON_INFO_SI_CP_DMA_COMPUTE:
*value = 1; *value = 1;
break; break;
case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
if (rdev->family >= CHIP_BONAIRE) {
*value = rdev->config.cik.backend_enable_mask;
} else if (rdev->family >= CHIP_TAHITI) {
*value = rdev->config.si.backend_enable_mask;
} else {
DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
}
break;
default: default:
DRM_DEBUG_KMS("Invalid request %d\n", info->request); DRM_DEBUG_KMS("Invalid request %d\n", info->request);
return -EINVAL; return -EINVAL;

2
drivers/gpu/drm/radeon/si.c
View File

@ -2855,6 +2855,8 @@ static void si_setup_rb(struct radeon_device *rdev,
mask <<= 1; mask <<= 1;
} }
rdev->config.si.backend_enable_mask = enabled_rbs;
for (i = 0; i < se_num; i++) { for (i = 0; i < se_num; i++) {
si_select_se_sh(rdev, i, 0xffffffff); si_select_se_sh(rdev, i, 0xffffffff);
data = 0; data = 0;

2
include/uapi/drm/radeon_drm.h
View File

@ -983,6 +983,8 @@ struct drm_radeon_cs {
#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
/* CIK macrotile mode array */ /* CIK macrotile mode array */
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
/* query the number of render backends */
#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
struct drm_radeon_info { struct drm_radeon_info {