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drm/i915/mtl: Update cache coherency setting for context structure

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As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.

Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
CC: Fei Yang <fei.yang@intel.com>
Reviewed-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com
This commit is contained in:
Zhanjun Dong 2023-07-06 10:47:04 -07:00 committed by Daniele Ceraolo Spurio
parent 2f42c5afb3
commit 43aa755eae
1 changed files with 8 additions and 1 deletions
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9
drivers/gpu/drm/i915/gt/intel_lrc.c
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@ -1092,8 +1092,15 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
obj = i915_gem_object_create_lmem(engine->i915, context_size,
I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
/*
* Wa_22016122933: For MTL the shared memory needs to be mapped
* as WC on CPU side and UC (PAT index 2) on GPU side
*/
if (IS_METEORLAKE(engine->i915))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
}
if (IS_ERR(obj))
return ERR_CAST(obj);