Mediatek DRM Next for Linux 5.14
1. Add MT8167 HDMI support 2. Fix PM reference leak 3. Add MT8183 DPI dual edge support -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAmDKDhkYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4kasoQAIkcqsKkALyOqLqa/T3NjWuv KNFre4g6f9MWD/qQEZvXkajE2isF+zk7PfYu5RzQw2w2OTRw8OZFqKDd3NrIV/5B 4PcR07b4t8oRlwShUB6e/H0cTO+O1SQqOGq6wtN0B55kcnkm3lB6DYQpvFH7MwGL bSRT+bkfIpFfas8HjbOSi8++j6DBZ3uvRpQECbvJEdal//x4bMLOb8ka37w+xoOz 1A7ASR3ydXodtnvNmXj0QV9ugMrpbaDmOGgOn0We2xGCr/3wsZRnRok69+S3buOZ 6yu6N+594gsk1gbTQRyb+9SXow67zTBwSK9dz5H5CPoIoX2q15lZp3rd4Ufud6jw Usu7OmK9HqC2BnGgiPyHSn8PTiQ3pW5stTalnz/YNKhNXcpd3XvU45tb0U0Qb364 o2C7hcJMTHKNgC42tdaxTlGwA+eHEManHwCeKTUeySWyHrRHeAXeZ4DrLpcj+l7t VsGIB7varcdTSrlg6fqnolFjOh0g44mEQwNey1TI5tpWL/Ol/fLuxzlfoK2GLRIO 47AlXqz/8sHcieeRhiaVXAuiKB79G+kS+NafYAe/KtlXG9/cEI7dZb8zSRYRMJR5 DwWODRFwMmTK2iFi2o1gEUZFNLIlpLn2XZNbJiVXl8V6L7qguqkMVvtNJEBvpPgk 2iipz2CQt6jf1QXbML/f =Splb -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.14 1. Add MT8167 HDMI support 2. Fix PM reference leak 3. Add MT8183 DPI dual edge support Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210616150301.292-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
commit
43ccc7831f
@ -0,0 +1,52 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek HDMI CEC Controller Device Tree Bindings
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maintainers:
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- CK Hu <ck.hu@mediatek.com>
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- Jitao shi <jitao.shi@mediatek.com>
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description: |
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The HDMI CEC controller handles hotplug detection and CEC communication.
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properties:
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compatible:
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enum:
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- mediatek,mt7623-cec
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- mediatek,mt8167-cec
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- mediatek,mt8173-cec
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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cec: cec@10013000 {
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compatible = "mediatek,mt8173-cec";
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reg = <0x10013000 0xbc>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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};
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...
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@ -0,0 +1,58 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek HDMI DDC Device Tree Bindings
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maintainers:
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- CK Hu <ck.hu@mediatek.com>
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- Jitao shi <jitao.shi@mediatek.com>
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description: |
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The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
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properties:
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compatible:
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enum:
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- mediatek,mt7623-hdmi-ddc
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- mediatek,mt8167-hdmi-ddc
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- mediatek,mt8173-hdmi-ddc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: ddc-i2c
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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hdmi_ddc0: i2c@11012000 {
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compatible = "mediatek,mt8173-hdmi-ddc";
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reg = <0x11012000 0x1c>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_I2C5>;
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clock-names = "ddc-i2c";
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};
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...
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@ -1,136 +0,0 @@
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Mediatek HDMI Encoder
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=====================
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The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
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its parallel input.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi".
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- the supported chips are mt2701, mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
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- phys: phandle link to the HDMI PHY node.
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See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
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- phy-names: must contain "hdmi"
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- mediatek,syscon-hdmi: phandle link and register offset to the system
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configuration registers. For mt8173 this must be offset 0x900 into the
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MMSYS_CONFIG region: <&mmsys 0x900>.
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- ports: A node containing input and output port nodes with endpoint
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definitions as documented in Documentation/devicetree/bindings/graph.txt.
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- port@0: The input port in the ports node should be connected to a DPI output
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port.
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- port@1: The output port in the ports node should be connected to the input
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port of a connector node that contains a ddc-i2c-bus property, or to the
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input port of an attached bridge chip, such as a SlimPort transmitter.
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HDMI CEC
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========
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The HDMI CEC controller handles hotplug detection and CEC communication.
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Required properties:
|
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- compatible: Should be "mediatek,<chip>-cec"
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- the supported chips are mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clock
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HDMI DDC
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========
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The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
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The Mediatek's I2C controller is used to interface with I2C devices.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi-ddc"
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- the supported chips are mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- clocks: device clock
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- clock-names: Should be "ddc-i2c".
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HDMI PHY
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========
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See phy/mediatek,hdmi-phy.yaml
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Example:
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cec: cec@10013000 {
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compatible = "mediatek,mt8173-cec";
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reg = <0 0x10013000 0 0xbc>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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};
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hdmi_phy: hdmi-phy@10209100 {
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compatible = "mediatek,mt8173-hdmi-phy";
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reg = <0 0x10209100 0 0x24>;
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clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
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clock-names = "pll_ref";
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clock-output-names = "hdmitx_dig_cts";
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mediatek,ibias = <0xa>;
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mediatek,ibias_up = <0x1c>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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hdmi_ddc0: i2c@11012000 {
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compatible = "mediatek,mt8173-hdmi-ddc";
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reg = <0 0x11012000 0 0x1c>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_I2C5>;
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clock-names = "ddc-i2c";
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};
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hdmi0: hdmi@14025000 {
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compatible = "mediatek,mt8173-hdmi";
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reg = <0 0x14025000 0 0x400>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLLCK>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pin>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
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assigned-clock-parents = <&hdmi_phy>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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};
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};
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connector {
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compatible = "hdmi-connector";
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type = "a";
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ddc-i2c-bus = <&hdmiddc0>;
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi0_out>;
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};
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};
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};
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@ -0,0 +1,133 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek HDMI Encoder Device Tree Bindings
|
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maintainers:
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- CK Hu <ck.hu@mediatek.com>
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- Jitao shi <jitao.shi@mediatek.com>
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description: |
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The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
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its parallel input.
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properties:
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compatible:
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enum:
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- mediatek,mt2701-hdmi
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- mediatek,mt7623-hdmi
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- mediatek,mt8167-hdmi
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- mediatek,mt8173-hdmi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Pixel Clock
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- description: HDMI PLL
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- description: Bit Clock
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- description: S/PDIF Clock
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clock-names:
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items:
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- const: pixel
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- const: pll
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- const: bclk
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- const: spdif
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: hdmi
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mediatek,syscon-hdmi:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: |
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phandle link and register offset to the system configuration registers.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Input port node. This port should be connected to a DPI output port.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Output port node. This port should be connected to the input port of a connector
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node that contains a ddc-i2c-bus property, or to the input port of an attached
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bridge chip, such as a SlimPort transmitter.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- mediatek,syscon-hdmi
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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hdmi0: hdmi@14025000 {
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compatible = "mediatek,mt8173-hdmi";
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reg = <0x14025000 0x400>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLLCK>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pin>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_con_in>;
|
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};
|
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};
|
||||
};
|
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};
|
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|
||||
...
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@ -83,6 +83,7 @@ struct mtk_dpi {
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_gpio;
|
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struct pinctrl_state *pins_dpi;
|
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u32 output_fmt;
|
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int refcount;
|
||||
};
|
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|
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@ -122,6 +123,8 @@ struct mtk_dpi_conf {
|
||||
u32 reg_h_fre_con;
|
||||
u32 max_clock_khz;
|
||||
bool edge_sel_en;
|
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const u32 *output_fmts;
|
||||
u32 num_output_fmts;
|
||||
};
|
||||
|
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static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
|
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@ -381,6 +384,20 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
|
||||
}
|
||||
}
|
||||
|
||||
static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
|
||||
{
|
||||
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
|
||||
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
|
||||
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
|
||||
DDR_EN | DDR_4PHASE);
|
||||
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
|
||||
dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
|
||||
EDGE_SEL : 0, EDGE_SEL);
|
||||
} else {
|
||||
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void mtk_dpi_power_off(struct mtk_dpi *dpi)
|
||||
{
|
||||
if (WARN_ON(dpi->refcount == 0))
|
||||
@ -455,7 +472,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
|
||||
pll_rate = clk_get_rate(dpi->tvd_clk);
|
||||
|
||||
vm.pixelclock = pll_rate / factor;
|
||||
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
|
||||
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
|
||||
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
|
||||
clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
|
||||
else
|
||||
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
|
||||
|
||||
|
||||
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
|
||||
|
||||
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
|
||||
@ -519,12 +542,87 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
|
||||
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
|
||||
mtk_dpi_config_color_format(dpi, dpi->color_format);
|
||||
mtk_dpi_config_2n_h_fre(dpi);
|
||||
mtk_dpi_dual_edge(dpi);
|
||||
mtk_dpi_config_disable_edge(dpi);
|
||||
mtk_dpi_sw_reset(dpi, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state,
|
||||
unsigned int *num_output_fmts)
|
||||
{
|
||||
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
||||
u32 *output_fmts;
|
||||
|
||||
*num_output_fmts = 0;
|
||||
|
||||
if (!dpi->conf->output_fmts) {
|
||||
dev_err(dpi->dev, "output_fmts should not be null\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
|
||||
GFP_KERNEL);
|
||||
if (!output_fmts)
|
||||
return NULL;
|
||||
|
||||
*num_output_fmts = dpi->conf->num_output_fmts;
|
||||
|
||||
memcpy(output_fmts, dpi->conf->output_fmts,
|
||||
sizeof(*output_fmts) * dpi->conf->num_output_fmts);
|
||||
|
||||
return output_fmts;
|
||||
}
|
||||
|
||||
static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state,
|
||||
u32 output_fmt,
|
||||
unsigned int *num_input_fmts)
|
||||
{
|
||||
u32 *input_fmts;
|
||||
|
||||
*num_input_fmts = 0;
|
||||
|
||||
input_fmts = kcalloc(1, sizeof(*input_fmts),
|
||||
GFP_KERNEL);
|
||||
if (!input_fmts)
|
||||
return NULL;
|
||||
|
||||
*num_input_fmts = 1;
|
||||
input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
|
||||
return input_fmts;
|
||||
}
|
||||
|
||||
static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct mtk_dpi *dpi = bridge->driver_private;
|
||||
unsigned int out_bus_format;
|
||||
|
||||
out_bus_format = bridge_state->output_bus_cfg.format;
|
||||
|
||||
dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
|
||||
bridge_state->input_bus_cfg.format,
|
||||
bridge_state->output_bus_cfg.format);
|
||||
|
||||
dpi->output_fmt = out_bus_format;
|
||||
dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
|
||||
dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
|
||||
dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
|
||||
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
|
||||
enum drm_bridge_attach_flags flags)
|
||||
{
|
||||
@ -577,6 +675,12 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
|
||||
.mode_valid = mtk_dpi_bridge_mode_valid,
|
||||
.disable = mtk_dpi_bridge_disable,
|
||||
.enable = mtk_dpi_bridge_enable,
|
||||
.atomic_check = mtk_dpi_bridge_atomic_check,
|
||||
.atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
|
||||
.atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
|
||||
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
||||
.atomic_reset = drm_atomic_helper_bridge_reset,
|
||||
};
|
||||
|
||||
void mtk_dpi_start(struct device *dev)
|
||||
@ -623,11 +727,6 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
|
||||
}
|
||||
drm_connector_attach_encoder(dpi->connector, &dpi->encoder);
|
||||
|
||||
dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
|
||||
dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
|
||||
dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
|
||||
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup:
|
||||
@ -680,10 +779,21 @@ static unsigned int mt8183_calculate_factor(int clock)
|
||||
return 2;
|
||||
}
|
||||
|
||||
static const u32 mt8173_output_fmts[] = {
|
||||
MEDIA_BUS_FMT_RGB888_1X24,
|
||||
};
|
||||
|
||||
static const u32 mt8183_output_fmts[] = {
|
||||
MEDIA_BUS_FMT_RGB888_2X12_LE,
|
||||
MEDIA_BUS_FMT_RGB888_2X12_BE,
|
||||
};
|
||||
|
||||
static const struct mtk_dpi_conf mt8173_conf = {
|
||||
.cal_factor = mt8173_calculate_factor,
|
||||
.reg_h_fre_con = 0xe0,
|
||||
.max_clock_khz = 300000,
|
||||
.output_fmts = mt8173_output_fmts,
|
||||
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
|
||||
};
|
||||
|
||||
static const struct mtk_dpi_conf mt2701_conf = {
|
||||
@ -691,18 +801,24 @@ static const struct mtk_dpi_conf mt2701_conf = {
|
||||
.reg_h_fre_con = 0xb0,
|
||||
.edge_sel_en = true,
|
||||
.max_clock_khz = 150000,
|
||||
.output_fmts = mt8173_output_fmts,
|
||||
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
|
||||
};
|
||||
|
||||
static const struct mtk_dpi_conf mt8183_conf = {
|
||||
.cal_factor = mt8183_calculate_factor,
|
||||
.reg_h_fre_con = 0xe0,
|
||||
.max_clock_khz = 100000,
|
||||
.output_fmts = mt8183_output_fmts,
|
||||
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
|
||||
};
|
||||
|
||||
static const struct mtk_dpi_conf mt8192_conf = {
|
||||
.cal_factor = mt8183_calculate_factor,
|
||||
.reg_h_fre_con = 0xe0,
|
||||
.max_clock_khz = 150000,
|
||||
.output_fmts = mt8173_output_fmts,
|
||||
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
|
||||
};
|
||||
|
||||
static int mtk_dpi_probe(struct platform_device *pdev)
|
||||
@ -718,6 +834,7 @@ static int mtk_dpi_probe(struct platform_device *pdev)
|
||||
|
||||
dpi->dev = dev;
|
||||
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
|
||||
dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
|
||||
dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
|
||||
if (IS_ERR(dpi->pinctrl)) {
|
||||
|
||||
@ -260,7 +260,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
|
||||
drm_connector_list_iter_end(&conn_iter);
|
||||
}
|
||||
|
||||
ret = pm_runtime_get_sync(crtc->dev->dev);
|
||||
ret = pm_runtime_resume_and_get(crtc->dev->dev);
|
||||
if (ret < 0) {
|
||||
DRM_ERROR("Failed to enable power domain: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
@ -148,6 +148,8 @@ struct hdmi_audio_param {
|
||||
|
||||
struct mtk_hdmi_conf {
|
||||
bool tz_disabled;
|
||||
bool cea_modes_only;
|
||||
unsigned long max_mode_clock;
|
||||
};
|
||||
|
||||
struct mtk_hdmi {
|
||||
@ -1222,6 +1224,13 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
|
||||
return MODE_BAD;
|
||||
}
|
||||
|
||||
if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
|
||||
return MODE_BAD;
|
||||
|
||||
if (hdmi->conf->max_mode_clock &&
|
||||
mode->clock > hdmi->conf->max_mode_clock)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
if (mode->clock < 27000)
|
||||
return MODE_CLOCK_LOW;
|
||||
if (mode->clock > 297000)
|
||||
@ -1778,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
|
||||
.tz_disabled = true,
|
||||
};
|
||||
|
||||
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
|
||||
.max_mode_clock = 148500,
|
||||
.cea_modes_only = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt2701-hdmi",
|
||||
.data = &mtk_hdmi_conf_mt2701,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8167-hdmi",
|
||||
.data = &mtk_hdmi_conf_mt8167,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8173-hdmi",
|
||||
},
|
||||
{}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user